[llvm] [RISCV] Implement Intrinsics and CodeGen Support for XCValu Extension… (PR #78138)

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git-clang-format --diff 6752f1517dcfa7e54271c98459a3d52c823c0d60 0c00753fbc8771c5fa3ac6bb060c26a90d6460de -- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index aaac5ce834..77b5a6c7fb 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -53,8 +53,10 @@ private:
                             MachineBasicBlock::iterator MBBI);
   bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI);
-  bool expandCoreVClip(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
-  bool expandCoreVAddSub(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
+  bool expandCoreVClip(MachineBasicBlock &MBB,
+                       MachineBasicBlock::iterator MBBI);
+  bool expandCoreVAddSub(MachineBasicBlock &MBB,
+                         MachineBasicBlock::iterator MBBI);
 #ifndef NDEBUG
   unsigned getInstSizeInBytes(const MachineFunction &MF) const {
     unsigned Size = 0;
@@ -164,7 +166,8 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
     // vmset.m vd => vmxnor.mm vd, vd, vd
     return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
   case RISCV::CV_CLIP_PSEUDO:
-  case RISCV::CV_CLIPU_PSEUDO:return expandCoreVClip(MBB, MBBI);
+  case RISCV::CV_CLIPU_PSEUDO:
+    return expandCoreVClip(MBB, MBBI);
   case RISCV::CV_ADDN_PSEUDO:
   case RISCV::CV_ADDUN_PSEUDO:
   case RISCV::CV_ADDRN_PSEUDO:
@@ -172,7 +175,8 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
   case RISCV::CV_SUBN_PSEUDO:
   case RISCV::CV_SUBUN_PSEUDO:
   case RISCV::CV_SUBRN_PSEUDO:
-  case RISCV::CV_SUBURN_PSEUDO:return expandCoreVAddSub(MBB, MBBI);
+  case RISCV::CV_SUBURN_PSEUDO:
+    return expandCoreVAddSub(MBB, MBBI);
   }
 
   return false;
@@ -566,8 +570,9 @@ bool RISCVExpandPseudo::expandCoreVClip(llvm::MachineBasicBlock &MBB,
   Register I = MBBI->getOperand(1).getReg();
   uint64_t J = MBBI->getOperand(2).getImm();
 
-  unsigned Opcode = MBBI->getOpcode() == RISCV::CV_CLIPU_PSEUDO ?
-                    RISCV::CV_CLIPU : RISCV::CV_CLIP;
+  unsigned Opcode = MBBI->getOpcode() == RISCV::CV_CLIPU_PSEUDO
+                        ? RISCV::CV_CLIPU
+                        : RISCV::CV_CLIP;
   const MCInstrDesc &Desc = TII->get(Opcode);
   BuildMI(MBB, MBBI, DL, Desc, DstReg)
       .addReg(I)
@@ -612,19 +617,15 @@ bool RISCVExpandPseudo::expandCoreVAddSub(llvm::MachineBasicBlock &MBB,
   case RISCV::CV_SUBURN_PSEUDO:
     Opcode = IsImm ? RISCV::CV_SUBURN : RISCV::CV_SUBURNR;
     break;
-  default:llvm_unreachable("unknown instruction");
+  default:
+    llvm_unreachable("unknown instruction");
   }
   const MCInstrDesc &Desc = TII->get(Opcode);
   if (IsImm) {
-    BuildMI(MBB, MBBI, DL, Desc, DstReg).
-        addReg(X).
-        addReg(Y).
-        addImm(Shift);
+    BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(X).addReg(Y).addImm(Shift);
   } else {
     MRI->replaceRegWith(DstReg, X);
-    BuildMI(MBB, MBBI, DL, Desc, DstReg).
-        addReg(Y).
-        addReg(DstReg);
+    BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(Y).addReg(DstReg);
   }
   MBBI->eraseFromParent();
   return true;

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https://github.com/llvm/llvm-project/pull/78138