[llvm] [RISCV] Add scheduler model for sifive-p450. (PR #77989)

[Craig Topper via llvm-commits]

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@@ -36,6 +36,7 @@ include "GISel/RISCVRegisterBanks.td"
 
 include "RISCVSchedRocket.td"
 include "RISCVSchedSiFive7.td"
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topperc wrote:

> but there are some different designs I see from current scheduling model, which makes X280 and SiFive7 independent enough.

I'm not sure what different designs you're referring to here?

https://github.com/llvm/llvm-project/pull/77989