[llvm] [clang] riscv vector cc (PR #77560)
Brandon Wu via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 14 22:28:50 PST 2024
================
@@ -24,6 +24,19 @@ def CSR_ILP32D_LP64D
: CalleeSavedRegs<(add CSR_ILP32_LP64,
F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
+defvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31),
+ V2M2, V4M2, V6M2, V24M2, V26M2, V28M2, V30M2,
----------------
4vtomat wrote:
If I don't list all of LMUL variations, it would use LMUL 1 for all saved/restored registers, I'm not sure if we have any mechanism to auto-combine them?
https://github.com/llvm/llvm-project/pull/77560
More information about the llvm-commits
mailing list