[llvm] [RISCV] Add scheduler model for sifive-p450. (PR #77989)

[Wang Pengcheng via llvm-commits]

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@@ -153,6 +153,7 @@ Changes to the RISC-V Backend
   "SiFive Custom Instruction Extension" as SiFive defines it. The LLVM project
   needs to work with SiFive to define and document real extension names for
   individual CSRs and instructions.
+* ``-mcpu=sifive-p450`` was added.
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wangpc-pp wrote:

> I can commit this directly if you prefer?

Yes, that's OK.

https://github.com/llvm/llvm-project/pull/77989