[llvm] [RISCV] Add scheduler model for sifive-p450. (PR #77989)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,356 @@
+//==- RISCVSchedSiFiveP400.td - SiFiveP400 Scheduling Defs ---*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+
+// SiFiveP400 machine model for scheduling and other instruction cost heuristics.
+// https://github.com/sifive/federation/blob/master/specs/design/standard/u84.json
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topperc wrote:

Yes. I should remove that. It was copied from our internal repo

https://github.com/llvm/llvm-project/pull/77989