[llvm] 7528cf5 - [Target] Use getConstantOperandVal (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 14 00:53:40 PST 2024
Author: Kazu Hirata
Date: 2024-01-14T00:53:29-08:00
New Revision: 7528cf5ef23e392110e8d58ac2ccf7610123d889
URL: https://github.com/llvm/llvm-project/commit/7528cf5ef23e392110e8d58ac2ccf7610123d889
DIFF: https://github.com/llvm/llvm-project/commit/7528cf5ef23e392110e8d58ac2ccf7610123d889.diff
LOG: [Target] Use getConstantOperandVal (NFC)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 91b36161ab46e8..c27c5089c3e6cc 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -2164,9 +2164,8 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
break;
}
case AArch64ISD::MOVI: {
- ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(0));
- Known =
- KnownBits::makeConstant(APInt(Known.getBitWidth(), CN->getZExtValue()));
+ Known = KnownBits::makeConstant(
+ APInt(Known.getBitWidth(), Op->getConstantOperandVal(0)));
break;
}
case AArch64ISD::LOADgot:
@@ -2183,8 +2182,8 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
break;
}
case ISD::INTRINSIC_W_CHAIN: {
- ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
- Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
+ Intrinsic::ID IntID =
+ static_cast<Intrinsic::ID>(Op->getConstantOperandVal(1));
switch (IntID) {
default: return;
case Intrinsic::aarch64_ldaxr:
@@ -22284,8 +22283,8 @@ static SDValue performSETCCCombine(SDNode *N,
isNullConstant(LHS->getOperand(0)) && isOneConstant(LHS->getOperand(1)) &&
LHS->hasOneUse()) {
// Invert CSEL's condition.
- auto *OpCC = cast<ConstantSDNode>(LHS.getOperand(2));
- auto OldCond = static_cast<AArch64CC::CondCode>(OpCC->getZExtValue());
+ auto OldCond =
+ static_cast<AArch64CC::CondCode>(LHS.getConstantOperandVal(2));
auto NewCond = getInvertedCondCode(OldCond);
// csel 0, 1, !cond, X
@@ -24717,8 +24716,8 @@ void AArch64TargetLowering::ReplaceNodeResults(
assert((VT == MVT::i8 || VT == MVT::i16) &&
"custom lowering for unexpected type");
- ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(0));
- Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
+ Intrinsic::ID IntID =
+ static_cast<Intrinsic::ID>(N->getConstantOperandVal(0));
switch (IntID) {
default:
return;
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index 674fd04f2fc1c7..159b2d440b31a6 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -1619,8 +1619,7 @@ static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
for (unsigned i = 0; i < 4; i++) {
RemapSwizzle[i] = i;
if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- unsigned Idx = cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
- ->getZExtValue();
+ unsigned Idx = NewBldVec[i].getConstantOperandVal(1);
if (i == Idx)
isUnmovable[Idx] = true;
}
@@ -1628,8 +1627,7 @@ static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
for (unsigned i = 0; i < 4; i++) {
if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- unsigned Idx = cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
- ->getZExtValue();
+ unsigned Idx = NewBldVec[i].getConstantOperandVal(1);
if (isUnmovable[Idx])
continue;
// Swap i and Idx
@@ -2002,9 +2000,7 @@ bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx,
if (RegisterSDNode *Reg =
dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
if (Reg->getReg() == R600::ALU_CONST) {
- ConstantSDNode *Cst
- = cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
- Consts.push_back(Cst->getZExtValue());
+ Consts.push_back(ParentNode->getConstantOperandVal(OtherSelIdx));
}
}
}
@@ -2044,8 +2040,7 @@ bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx,
ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
}
} else {
- ConstantSDNode *C = cast<ConstantSDNode>(Src.getOperand(0));
- uint64_t Value = C->getZExtValue();
+ uint64_t Value = Src.getConstantOperandVal(0);
if (Value == 0) {
ImmReg = R600::ZERO;
} else if (Value == 1) {
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 3852f93da98dc4..a7f924114ed86c 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5742,8 +5742,7 @@ SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,
static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,
SDNode *N, SelectionDAG &DAG) {
EVT VT = N->getValueType(0);
- const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
- unsigned CondCode = CD->getZExtValue();
+ unsigned CondCode = N->getConstantOperandVal(3);
if (!ICmpInst::isIntPredicate(static_cast<ICmpInst::Predicate>(CondCode)))
return DAG.getUNDEF(VT);
@@ -5777,9 +5776,8 @@ static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,
static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI,
SDNode *N, SelectionDAG &DAG) {
EVT VT = N->getValueType(0);
- const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
- unsigned CondCode = CD->getZExtValue();
+ unsigned CondCode = N->getConstantOperandVal(3);
if (!FCmpInst::isFPPredicate(static_cast<FCmpInst::Predicate>(CondCode)))
return DAG.getUNDEF(VT);
@@ -7419,9 +7417,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
NumVDataDwords = Is64Bit ? 2 : 1;
}
} else {
- auto *DMaskConst =
- cast<ConstantSDNode>(Op.getOperand(ArgOffset + Intr->DMaskIndex));
- DMask = DMaskConst->getZExtValue();
+ DMask = Op->getConstantOperandVal(ArgOffset + Intr->DMaskIndex);
DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask);
if (BaseOpcode->Store) {
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index f8a281032c77b6..23852cf4979f53 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4246,8 +4246,7 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *Subtarget) {
SDLoc dl(Op);
- ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
- auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
+ auto SSID = static_cast<SyncScope::ID>(Op.getConstantOperandVal(2));
if (SSID == SyncScope::SingleThread)
return Op;
@@ -4261,8 +4260,8 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
DAG.getConstant(0, dl, MVT::i32));
}
- ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
- AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
+ AtomicOrdering Ord =
+ static_cast<AtomicOrdering>(Op.getConstantOperandVal(1));
ARM_MB::MemBOpt Domain = ARM_MB::ISH;
if (Subtarget->isMClass()) {
// Only a full system barrier exists in the M-class architectures.
@@ -20087,8 +20086,8 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
return;
}
case ISD::INTRINSIC_W_CHAIN: {
- ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
- Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
+ Intrinsic::ID IntID =
+ static_cast<Intrinsic::ID>(Op->getConstantOperandVal(1));
switch (IntID) {
default: return;
case Intrinsic::arm_ldaex:
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index defb1f7324f4e2..e4127b0b94c625 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -701,8 +701,7 @@ void HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
void HexagonDAGToDAGISel::SelectExtractSubvector(SDNode *N) {
SDValue Inp = N->getOperand(0);
MVT ResTy = N->getValueType(0).getSimpleVT();
- auto IdxN = cast<ConstantSDNode>(N->getOperand(1));
- unsigned Idx = IdxN->getZExtValue();
+ unsigned Idx = N->getConstantOperandVal(1);
[[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT();
[[maybe_unused]] unsigned ResLen = ResTy.getVectorNumElements();
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
index fb156f2583e8a9..ec5435949ae4a7 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
@@ -2573,8 +2573,7 @@ SDValue HvxSelector::getVectorConstant(ArrayRef<uint8_t> Data,
void HvxSelector::selectExtractSubvector(SDNode *N) {
SDValue Inp = N->getOperand(0);
MVT ResTy = N->getValueType(0).getSimpleVT();
- auto IdxN = cast<ConstantSDNode>(N->getOperand(1));
- unsigned Idx = IdxN->getZExtValue();
+ unsigned Idx = N->getConstantOperandVal(1);
[[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT();
[[maybe_unused]] unsigned ResLen = ResTy.getVectorNumElements();
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 34c5569b8076e3..6b4d2168e74938 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -5262,9 +5262,7 @@ static SDValue PerformANDCombine(SDNode *N,
return SDValue();
}
- unsigned ExtType =
- cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
- getZExtValue();
+ unsigned ExtType = Val->getConstantOperandVal(Val->getNumOperands() - 1);
if (ExtType == ISD::SEXTLOAD) {
// If for some reason the load is a sextload, the and is needed to zero
// out the high 8 bits
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 7d387c7b9f2f77..896091d3d4475b 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -6046,8 +6046,7 @@ SDValue SystemZTargetLowering::lowerIS_FPCLASS(SDValue Op,
SDLoc DL(Op);
MVT ResultVT = Op.getSimpleValueType();
SDValue Arg = Op.getOperand(0);
- auto CNode = cast<ConstantSDNode>(Op.getOperand(1));
- unsigned Check = CNode->getZExtValue();
+ unsigned Check = Op.getConstantOperandVal(1);
unsigned TDCMask = 0;
if (Check & fcSNan)
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 53ce720be2da4c..26149530b79aed 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2355,8 +2355,7 @@ SDValue X86DAGToDAGISel::matchIndexRecursively(SDValue N,
Src.hasOneUse()) {
if (CurDAG->isBaseWithConstantOffset(Src)) {
SDValue AddSrc = Src.getOperand(0);
- auto *AddVal = cast<ConstantSDNode>(Src.getOperand(1));
- uint64_t Offset = (uint64_t)AddVal->getZExtValue();
+ uint64_t Offset = Src.getConstantOperandVal(1);
if (!foldOffsetIntoAddress(Offset * AM.Scale, AM)) {
SDLoc DL(N);
SDValue Res;
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