[llvm] [X86] Use RORX over SHR imm (PR #77964)
Bryce Wilson via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 12 14:05:18 PST 2024
https://github.com/Bryce-MW updated https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson <bryce.wilson at oldmissioncapital.com>
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH] [X86] Use RORX over SHR imm
---
llvm/lib/Target/X86/X86InstrShiftRotate.td | 78 ++++++++++++++
llvm/test/CodeGen/X86/atomic-unordered.ll | 3 +-
llvm/test/CodeGen/X86/bmi2.ll | 6 +-
llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll | 3 +-
llvm/test/CodeGen/X86/pr35636.ll | 4 +-
llvm/test/CodeGen/X86/vector-trunc-ssat.ll | 116 ++++++++++-----------
6 files changed, 143 insertions(+), 67 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td
index f951894db1890c..238e8e9b6e97f3 100644
--- a/llvm/lib/Target/X86/X86InstrShiftRotate.td
+++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td
@@ -879,6 +879,26 @@ let Predicates = [HasBMI2, HasEGPR, In64BitMode] in {
defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem, "_EVEX">, T8, PD, REX_W, EVEX;
}
+
+def immle16_8 : ImmLeaf<i8, [{
+ return Imm <= 16 - 8;
+}]>;
+def immle32_8 : ImmLeaf<i8, [{
+ return Imm <= 32 - 8;
+}]>;
+def immle64_8 : ImmLeaf<i8, [{
+ return Imm <= 64 - 8;
+}]>;
+def immle32_16 : ImmLeaf<i8, [{
+ return Imm <= 32 - 16;
+}]>;
+def immle64_16 : ImmLeaf<i8, [{
+ return Imm <= 64 - 16;
+}]>;
+def immle64_32 : ImmLeaf<i8, [{
+ return Imm <= 64 - 32;
+}]>;
+
let Predicates = [HasBMI2] in {
// Prefer RORX which is non-destructive and doesn't update EFLAGS.
let AddedComplexity = 10 in {
@@ -891,6 +911,64 @@ let Predicates = [HasBMI2] in {
(RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;
def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
(RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
+
+ // A right shift by less than a smaller register size that is then
+ // truncated to that register size can be replaced by RORX to
+ // preserve flags with the same execution cost
+
+ def : Pat<(i8 (trunc (srl GR16:$src, (i8 immle16_8:$shamt)))),
+ (EXTRACT_SUBREG (RORX32ri (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit), imm:$shamt), sub_8bit)>;
+ def : Pat<(i8 (trunc (sra GR16:$src, (i8 immle16_8:$shamt)))),
+ (EXTRACT_SUBREG (RORX32ri (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit), imm:$shamt), sub_8bit)>;
+ def : Pat<(i8 (trunc (srl GR32:$src, (i8 immle32_8:$shamt)))),
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_8bit)>;
+ def : Pat<(i8 (trunc (sra GR32:$src, (i8 immle32_8:$shamt)))),
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_8bit)>;
+ def : Pat<(i8 (trunc (srl GR64:$src, (i8 immle64_8:$shamt)))),
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_8bit)>;
+ def : Pat<(i8 (trunc (sra GR64:$src, (i8 immle64_8:$shamt)))),
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_8bit)>;
+
+
+ def : Pat<(i16 (trunc (srl GR32:$src, (i8 immle32_16:$shamt)))),
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_16bit)>;
+ def : Pat<(i16 (trunc (sra GR32:$src, (i8 immle32_16:$shamt)))),
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_16bit)>;
+ def : Pat<(i16 (trunc (srl GR64:$src, (i8 immle64_16:$shamt)))),
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_16bit)>;
+ def : Pat<(i16 (trunc (sra GR64:$src, (i8 immle64_16:$shamt)))),
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_16bit)>;
+
+ def : Pat<(i32 (trunc (srl GR64:$src, (i8 immle64_32:$shamt)))),
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_32bit)>;
+ def : Pat<(i32 (trunc (sra GR64:$src, (i8 immle64_32:$shamt)))),
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_32bit)>;
+
+
+ // Can't expand the load
+ def : Pat<(i8 (trunc (srl (loadi32 addr:$src), (i8 immle32_8:$shamt)))),
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_8bit)>;
+ def : Pat<(i8 (trunc (sra (loadi32 addr:$src), (i8 immle32_8:$shamt)))),
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_8bit)>;
+ def : Pat<(i8 (trunc (srl (loadi64 addr:$src), (i8 immle64_8:$shamt)))),
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_8bit)>;
+ def : Pat<(i8 (trunc (sra (loadi64 addr:$src), (i8 immle64_8:$shamt)))),
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_8bit)>;
+
+
+ def : Pat<(i16 (trunc (srl (loadi32 addr:$src), (i8 immle32_16:$shamt)))),
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_16bit)>;
+ def : Pat<(i16 (trunc (sra (loadi32 addr:$src), (i8 immle32_16:$shamt)))),
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_16bit)>;
+ def : Pat<(i16 (trunc (srl (loadi64 addr:$src), (i8 immle64_16:$shamt)))),
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_16bit)>;
+ def : Pat<(i16 (trunc (sra (loadi64 addr:$src), (i8 immle64_16:$shamt)))),
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_16bit)>;
+
+ def : Pat<(i32 (trunc (srl (loadi64 addr:$src), (i8 immle64_32:$shamt)))),
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_32bit)>;
+ def : Pat<(i32 (trunc (sra (loadi64 addr:$src), (i8 immle64_32:$shamt)))),
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_32bit)>;
}
def : Pat<(rotr (loadi32 addr:$src), (i8 imm:$shamt)),
diff --git a/llvm/test/CodeGen/X86/atomic-unordered.ll b/llvm/test/CodeGen/X86/atomic-unordered.ll
index df123be53474f0..c867817fd2dfff 100644
--- a/llvm/test/CodeGen/X86/atomic-unordered.ll
+++ b/llvm/test/CodeGen/X86/atomic-unordered.ll
@@ -2062,8 +2062,7 @@ define i32 @split_load(ptr %p) {
; CHECK-O3-LABEL: split_load:
; CHECK-O3: # %bb.0:
; CHECK-O3-NEXT: movq (%rdi), %rax
-; CHECK-O3-NEXT: movq %rax, %rcx
-; CHECK-O3-NEXT: shrq $32, %rcx
+; CHECK-O3-NEXT: rorxq $32, %rax, %rcx
; CHECK-O3-NEXT: orl %eax, %ecx
; CHECK-O3-NEXT: movzbl %cl, %eax
; CHECK-O3-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/bmi2.ll b/llvm/test/CodeGen/X86/bmi2.ll
index 24e38cfeb704df..e81434b35096ac 100644
--- a/llvm/test/CodeGen/X86/bmi2.ll
+++ b/llvm/test/CodeGen/X86/bmi2.ll
@@ -310,8 +310,7 @@ define i32 @mulx32(i32 %x, i32 %y, ptr %p) {
; X64-NEXT: addl %edi, %edi
; X64-NEXT: leal (%rsi,%rsi), %eax
; X64-NEXT: imulq %rdi, %rax
-; X64-NEXT: movq %rax, %rcx
-; X64-NEXT: shrq $32, %rcx
+; X64-NEXT: rorxq $32, %rax, %rcx
; X64-NEXT: movl %ecx, (%rdx)
; X64-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NEXT: retq
@@ -344,8 +343,7 @@ define i32 @mulx32_load(i32 %x, ptr %y, ptr %p) {
; X64-NEXT: leal (%rdi,%rdi), %eax
; X64-NEXT: movl (%rsi), %ecx
; X64-NEXT: imulq %rcx, %rax
-; X64-NEXT: movq %rax, %rcx
-; X64-NEXT: shrq $32, %rcx
+; X64-NEXT: rorxq $32, %rax, %rcx
; X64-NEXT: movl %ecx, (%rdx)
; X64-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll b/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
index 7996454a0158ea..a935bca3161b09 100644
--- a/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
+++ b/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
@@ -157,7 +157,8 @@ define i1 @shr_to_shl_eq_i16_s1_fail(i16 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: movzwl %di, %eax
; CHECK-NEXT: andl $32766, %edi # imm = 0x7FFE
-; CHECK-NEXT: shrl %eax
+; CHECK-NOBMI-NEXT: shrl %eax
+; CHECK-BMI2-NEXT: rorxl $1, %eax, %eax
; CHECK-NEXT: cmpw %ax, %di
; CHECK-NEXT: sete %al
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr35636.ll b/llvm/test/CodeGen/X86/pr35636.ll
index 0b7d64f38c7802..8b8a25eb5632c4 100644
--- a/llvm/test/CodeGen/X86/pr35636.ll
+++ b/llvm/test/CodeGen/X86/pr35636.ll
@@ -10,7 +10,7 @@ define void @_Z15uint64_to_asciimPc(i64 %arg) {
; HSW-NEXT: mulxq %rax, %rax, %rax
; HSW-NEXT: shrq $42, %rax
; HSW-NEXT: imulq $281474977, %rax, %rax # imm = 0x10C6F7A1
-; HSW-NEXT: shrq $20, %rax
+; HSW-NEXT: rorxq $20, %rax, %rax
; HSW-NEXT: leal (%rax,%rax,4), %eax
; HSW-NEXT: addl $5, %eax
; HSW-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF
@@ -27,7 +27,7 @@ define void @_Z15uint64_to_asciimPc(i64 %arg) {
; ZN-NEXT: mulxq %rax, %rax, %rax
; ZN-NEXT: shrq $42, %rax
; ZN-NEXT: imulq $281474977, %rax, %rax # imm = 0x10C6F7A1
-; ZN-NEXT: shrq $20, %rax
+; ZN-NEXT: rorxq $20, %rax, %rax
; ZN-NEXT: leal 5(%rax,%rax,4), %eax
; ZN-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF
; ZN-NEXT: leal (%rax,%rax,4), %eax
diff --git a/llvm/test/CodeGen/X86/vector-trunc-ssat.ll b/llvm/test/CodeGen/X86/vector-trunc-ssat.ll
index 14f724fc3b8c79..2837be16b6b2b0 100644
--- a/llvm/test/CodeGen/X86/vector-trunc-ssat.ll
+++ b/llvm/test/CodeGen/X86/vector-trunc-ssat.ll
@@ -4843,72 +4843,72 @@ define void @trunc_ssat_v16i32_v16i24(<16 x i32> %x, ptr %y) nounwind {
; SKX-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; SKX-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; SKX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
-; SKX-NEXT: vpextrd $3, %xmm1, %r15d
-; SKX-NEXT: movw %r15w, 45(%rdi)
-; SKX-NEXT: vpextrd $2, %xmm1, %r14d
-; SKX-NEXT: movw %r14w, 42(%rdi)
-; SKX-NEXT: vpextrd $1, %xmm1, %ebp
-; SKX-NEXT: movw %bp, 39(%rdi)
+; SKX-NEXT: vpextrd $3, %xmm1, %r8d
+; SKX-NEXT: movw %r8w, 45(%rdi)
+; SKX-NEXT: vpextrd $2, %xmm1, %r9d
+; SKX-NEXT: movw %r9w, 42(%rdi)
+; SKX-NEXT: vpextrd $1, %xmm1, %r10d
+; SKX-NEXT: movw %r10w, 39(%rdi)
; SKX-NEXT: vmovd %xmm1, %r11d
; SKX-NEXT: movw %r11w, 36(%rdi)
; SKX-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; SKX-NEXT: vpextrd $3, %xmm1, %ebx
; SKX-NEXT: movw %bx, 33(%rdi)
-; SKX-NEXT: vpextrd $2, %xmm1, %r10d
-; SKX-NEXT: movw %r10w, 30(%rdi)
-; SKX-NEXT: vpextrd $1, %xmm1, %r9d
-; SKX-NEXT: movw %r9w, 27(%rdi)
-; SKX-NEXT: vmovd %xmm1, %r8d
-; SKX-NEXT: vpextrd $3, %xmm0, %edx
-; SKX-NEXT: movw %r8w, 24(%rdi)
-; SKX-NEXT: movw %dx, 9(%rdi)
-; SKX-NEXT: vpextrd $2, %xmm0, %esi
-; SKX-NEXT: vpextrd $1, %xmm0, %eax
-; SKX-NEXT: movw %si, 6(%rdi)
-; SKX-NEXT: movw %ax, 3(%rdi)
-; SKX-NEXT: vmovd %xmm0, %ecx
-; SKX-NEXT: movw %cx, (%rdi)
-; SKX-NEXT: shrl $16, %r15d
-; SKX-NEXT: movb %r15b, 47(%rdi)
-; SKX-NEXT: shrl $16, %r14d
-; SKX-NEXT: movb %r14b, 44(%rdi)
-; SKX-NEXT: shrl $16, %ebp
-; SKX-NEXT: movb %bpl, 41(%rdi)
-; SKX-NEXT: shrl $16, %r11d
-; SKX-NEXT: movb %r11b, 38(%rdi)
-; SKX-NEXT: shrl $16, %ebx
-; SKX-NEXT: movb %bl, 35(%rdi)
-; SKX-NEXT: shrl $16, %r10d
-; SKX-NEXT: movb %r10b, 32(%rdi)
-; SKX-NEXT: shrl $16, %r9d
-; SKX-NEXT: movb %r9b, 29(%rdi)
-; SKX-NEXT: shrl $16, %r8d
+; SKX-NEXT: vpextrd $2, %xmm1, %ebp
+; SKX-NEXT: movw %bp, 30(%rdi)
+; SKX-NEXT: vpextrd $1, %xmm1, %r14d
+; SKX-NEXT: movw %r14w, 27(%rdi)
+; SKX-NEXT: vmovd %xmm1, %r15d
+; SKX-NEXT: vpextrd $3, %xmm0, %eax
+; SKX-NEXT: movw %r15w, 24(%rdi)
+; SKX-NEXT: movw %ax, 9(%rdi)
+; SKX-NEXT: vpextrd $2, %xmm0, %ecx
+; SKX-NEXT: vpextrd $1, %xmm0, %edx
+; SKX-NEXT: movw %cx, 6(%rdi)
+; SKX-NEXT: movw %dx, 3(%rdi)
+; SKX-NEXT: vmovd %xmm0, %esi
+; SKX-NEXT: movw %si, (%rdi)
+; SKX-NEXT: rorxl $16, %r8d, %r8d
+; SKX-NEXT: movb %r8b, 47(%rdi)
+; SKX-NEXT: rorxl $16, %r9d, %r8d
+; SKX-NEXT: movb %r8b, 44(%rdi)
+; SKX-NEXT: rorxl $16, %r10d, %r8d
+; SKX-NEXT: movb %r8b, 41(%rdi)
+; SKX-NEXT: rorxl $16, %r11d, %r8d
+; SKX-NEXT: movb %r8b, 38(%rdi)
+; SKX-NEXT: rorxl $16, %ebx, %r8d
+; SKX-NEXT: movb %r8b, 35(%rdi)
+; SKX-NEXT: rorxl $16, %ebp, %r8d
+; SKX-NEXT: movb %r8b, 32(%rdi)
+; SKX-NEXT: rorxl $16, %r14d, %r8d
+; SKX-NEXT: movb %r8b, 29(%rdi)
+; SKX-NEXT: rorxl $16, %r15d, %r8d
; SKX-NEXT: movb %r8b, 26(%rdi)
; SKX-NEXT: vextracti128 $1, %ymm0, %xmm0
-; SKX-NEXT: vpextrd $3, %xmm0, %r11d
-; SKX-NEXT: movw %r11w, 21(%rdi)
-; SKX-NEXT: vpextrd $2, %xmm0, %r10d
-; SKX-NEXT: movw %r10w, 18(%rdi)
-; SKX-NEXT: vpextrd $1, %xmm0, %r9d
-; SKX-NEXT: movw %r9w, 15(%rdi)
-; SKX-NEXT: vmovd %xmm0, %r8d
-; SKX-NEXT: movw %r8w, 12(%rdi)
-; SKX-NEXT: shrl $16, %edx
-; SKX-NEXT: movb %dl, 11(%rdi)
-; SKX-NEXT: shrl $16, %esi
-; SKX-NEXT: movb %sil, 8(%rdi)
-; SKX-NEXT: shrl $16, %eax
+; SKX-NEXT: vpextrd $3, %xmm0, %r8d
+; SKX-NEXT: movw %r8w, 21(%rdi)
+; SKX-NEXT: vpextrd $2, %xmm0, %r9d
+; SKX-NEXT: movw %r9w, 18(%rdi)
+; SKX-NEXT: vpextrd $1, %xmm0, %r10d
+; SKX-NEXT: movw %r10w, 15(%rdi)
+; SKX-NEXT: vmovd %xmm0, %r11d
+; SKX-NEXT: movw %r11w, 12(%rdi)
+; SKX-NEXT: rorxl $16, %eax, %eax
+; SKX-NEXT: movb %al, 11(%rdi)
+; SKX-NEXT: rorxl $16, %ecx, %eax
+; SKX-NEXT: movb %al, 8(%rdi)
+; SKX-NEXT: rorxl $16, %edx, %eax
; SKX-NEXT: movb %al, 5(%rdi)
-; SKX-NEXT: shrl $16, %ecx
-; SKX-NEXT: movb %cl, 2(%rdi)
-; SKX-NEXT: shrl $16, %r11d
-; SKX-NEXT: movb %r11b, 23(%rdi)
-; SKX-NEXT: shrl $16, %r10d
-; SKX-NEXT: movb %r10b, 20(%rdi)
-; SKX-NEXT: shrl $16, %r9d
-; SKX-NEXT: movb %r9b, 17(%rdi)
-; SKX-NEXT: shrl $16, %r8d
-; SKX-NEXT: movb %r8b, 14(%rdi)
+; SKX-NEXT: rorxl $16, %esi, %eax
+; SKX-NEXT: movb %al, 2(%rdi)
+; SKX-NEXT: rorxl $16, %r8d, %eax
+; SKX-NEXT: movb %al, 23(%rdi)
+; SKX-NEXT: rorxl $16, %r9d, %eax
+; SKX-NEXT: movb %al, 20(%rdi)
+; SKX-NEXT: rorxl $16, %r10d, %eax
+; SKX-NEXT: movb %al, 17(%rdi)
+; SKX-NEXT: rorxl $16, %r11d, %eax
+; SKX-NEXT: movb %al, 14(%rdi)
; SKX-NEXT: popq %rbx
; SKX-NEXT: popq %r14
; SKX-NEXT: popq %r15
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