[llvm] 9d8e538 - [AMDGPU] Refactor getNonSoftWaitcntOpcode and its callers (#77933)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 12 09:12:14 PST 2024
Author: Jay Foad
Date: 2024-01-12T17:12:09Z
New Revision: 9d8e53818ded8268da2df43e73880073fcf02922
URL: https://github.com/llvm/llvm-project/commit/9d8e53818ded8268da2df43e73880073fcf02922
DIFF: https://github.com/llvm/llvm-project/commit/9d8e53818ded8268da2df43e73880073fcf02922.diff
LOG: [AMDGPU] Refactor getNonSoftWaitcntOpcode and its callers (#77933)
This avoids listing all soft waitcnt opcodes in two places
(getNonSoftWaitcntOpcode and isSoftWaitcnt) and avoids the need for
helpers isWaitcnt and isWaitcntVsCnt.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 99cf661cc46d3e..acf9489b2d3772 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -874,11 +874,11 @@ static bool updateOperandIfDifferent(MachineInstr &MI, uint16_t OpName,
}
bool SIInsertWaitcnts::promoteSoftWaitCnt(MachineInstr *Waitcnt) const {
- unsigned Opcode = Waitcnt->getOpcode();
- if (!SIInstrInfo::isSoftWaitcnt(Opcode))
+ unsigned Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Waitcnt->getOpcode());
+ if (Opcode == Waitcnt->getOpcode())
return false;
- Waitcnt->setDesc(TII->get(SIInstrInfo::getNonSoftWaitcntOpcode(Opcode)));
+ Waitcnt->setDesc(TII->get(Opcode));
return true;
}
@@ -898,10 +898,10 @@ bool SIInsertWaitcnts::applyPreexistingWaitcnt(
if (II.isMetaInstruction())
continue;
- unsigned Opcode = II.getOpcode();
- bool IsSoft = SIInstrInfo::isSoftWaitcnt(Opcode);
+ unsigned Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(II.getOpcode());
+ bool IsSoft = Opcode != II.getOpcode();
- if (SIInstrInfo::isWaitcnt(Opcode)) {
+ if (Opcode == AMDGPU::S_WAITCNT) {
// Update required wait count. If this is a soft waitcnt (= it was added
// by an earlier pass), it may be entirely removed.
unsigned IEnc = II.getOperand(0).getImm();
@@ -918,7 +918,7 @@ bool SIInsertWaitcnts::applyPreexistingWaitcnt(
WaitcntInstr = ⅈ
} else {
- assert(SIInstrInfo::isWaitcntVsCnt(Opcode));
+ assert(Opcode == AMDGPU::S_WAITCNT_VSCNT);
assert(II.getOperand(0).getReg() == AMDGPU::SGPR_NULL);
unsigned OldVSCnt =
@@ -1590,9 +1590,9 @@ bool WaitcntBrackets::merge(const WaitcntBrackets &Other) {
}
static bool isWaitInstr(MachineInstr &Inst) {
- auto Opcode = Inst.getOpcode();
- return SIInstrInfo::isWaitcnt(Opcode) ||
- (SIInstrInfo::isWaitcntVsCnt(Opcode) && Inst.getOperand(0).isReg() &&
+ unsigned Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Inst.getOpcode());
+ return Opcode == AMDGPU::S_WAITCNT ||
+ (Opcode == AMDGPU::S_WAITCNT_VSCNT && Inst.getOperand(0).isReg() &&
Inst.getOperand(0).getReg() == AMDGPU::SGPR_NULL);
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index e50f5f28e03010..aa98a4b860dda9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -9076,8 +9076,7 @@ bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {
}
int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
- if (SIInstrInfo::isSoftWaitcnt(Opcode))
- Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Opcode);
+ Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Opcode);
unsigned Gen = subtargetEncodingFamily(ST);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 37ee159362a28c..daef6031dd0748 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -905,29 +905,14 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
}
static unsigned getNonSoftWaitcntOpcode(unsigned Opcode) {
- if (isWaitcnt(Opcode))
+ switch (Opcode) {
+ case AMDGPU::S_WAITCNT_soft:
return AMDGPU::S_WAITCNT;
-
- if (isWaitcntVsCnt(Opcode))
+ case AMDGPU::S_WAITCNT_VSCNT_soft:
return AMDGPU::S_WAITCNT_VSCNT;
-
- llvm_unreachable("Expected opcode S_WAITCNT/S_WAITCNT_VSCNT");
- }
-
- static bool isWaitcnt(unsigned Opcode) {
- return Opcode == AMDGPU::S_WAITCNT || Opcode == AMDGPU::S_WAITCNT_soft;
- }
-
- static bool isWaitcntVsCnt(unsigned Opcode) {
- return Opcode == AMDGPU::S_WAITCNT_VSCNT ||
- Opcode == AMDGPU::S_WAITCNT_VSCNT_soft;
- }
-
- // "Soft" waitcnt instructions can be relaxed/optimized out by
- // SIInsertWaitcnts.
- static bool isSoftWaitcnt(unsigned Opcode) {
- return Opcode == AMDGPU::S_WAITCNT_soft ||
- Opcode == AMDGPU::S_WAITCNT_VSCNT_soft;
+ default:
+ return Opcode;
+ }
}
bool isVGPRCopy(const MachineInstr &MI) const {
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