[llvm] [GlobalISel] Refactor extractParts() (PR #75223)

via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 12 09:07:27 PST 2024


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git-clang-format --diff f02b7770bb04b88455804b371dba1f44a86b90da 9d7e7e7810ae5cc9575216ff64a3aa8fadbb8619 -- llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h llvm/include/llvm/CodeGen/GlobalISel/Utils.h llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp llvm/lib/CodeGen/GlobalISel/Utils.cpp llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index b185d94518..aed826a9cb 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -507,7 +507,8 @@ bool llvm::extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy,
   }
 
   // Try to use unmerge for irregular vector split where possible
-  // For example when splitting a <6 x i32> into <4 x i32> with <2 x i32> leftover, it becomes:
+  // For example when splitting a <6 x i32> into <4 x i32> with <2 x i32>
+  // leftover, it becomes:
   //  <2 x i32> %2, <2 x i32>%3, <2 x i32> %4 = G_UNMERGE_VALUE <6 x i32> %1
   //  <4 x i32> %5 = G_CONCAT_VECTOR <2 x i32> %2, <2 x i32> %3
   if (RegTy.isVector() && MainTy.isVector()) {

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https://github.com/llvm/llvm-project/pull/75223


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