[llvm] [AMDGPU] Src1 of VOP3 DPP instructions can be SGPR on supported subtargets (PR #67461)

[Mirko Brkušanin via llvm-commits]

mbrkusanin wrote:

> @mbrkusanin @Sisyph it seems like this works for integer instructions:
> 
> ```
> $ llvm-mc -arch=amdgcn -mcpu=gfx1150 -show-encoding <<< "v_add_nc_u32_e64_dpp v5, v1, s3 quad_perm:[3,2,1,0]"
> 	.text
> 	v_add_nc_u32_e64_dpp v5, v1, s3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x06,0x00,0x00,0x01,0x1b,0x00,0xff]
> ```
> 
> but not for floating point:
> 
> ```
> $ llvm-mc -arch=amdgcn -mcpu=gfx1150 -show-encoding <<< "v_add_f32_e64_dpp v5, v1, s3 quad_perm:[3,2,1,0]"
> 	.text
> <stdin>:1:27: error: invalid operand for instruction
> v_add_f32_e64_dpp v5, v1, s3 quad_perm:[3,2,1,0]
>                           ^
> ```
> 
> Is that a bug or is there some reason for it?

A bug. Looks like class for src1_modifiers needs to be updated in tablegen, it differs for ints and floats. I'm working on a patch.

https://github.com/llvm/llvm-project/pull/67461