[llvm] [X86] Surpport APX promoted RAO-INT and MOVBE instructions (PR #77431)

[Shengchen Kan via llvm-commits]

================
@@ -1121,6 +1121,62 @@ let Predicates = [HasMOVBE] in {
   }
 }
 
+let Predicates = [HasMOVBE, HasEGPR, In64BitMode] in {
+  let SchedRW = [WriteALULd] in {
+  def MOVBE16rm_EVEX : I<0x60, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
+                         "movbe{w}\t{$src, $dst|$dst, $src}",
+                         [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>,
+                       EVEX, NoCD8, T_MAP4, PD;
+  def MOVBE32rm_EVEX : I<0x60, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
+                         "movbe{l}\t{$src, $dst|$dst, $src}",
+                         [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>,
+                       EVEX, NoCD8, T_MAP4;
+  def MOVBE64rm_EVEX : RI<0x60, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
+                         "movbe{q}\t{$src, $dst|$dst, $src}",
+                         [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>,
+                       EVEX, NoCD8, T_MAP4;
+  }
+  let SchedRW = [WriteStore] in {
+  def MOVBE16mr_EVEX : I<0x61, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
+                         "movbe{w}\t{$src, $dst|$dst, $src}",
+                         [(store (bswap GR16:$src), addr:$dst)]>,
+                       EVEX, NoCD8, T_MAP4, PD;
+  def MOVBE32mr_EVEX : I<0x61, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
+                         "movbe{l}\t{$src, $dst|$dst, $src}",
+                         [(store (bswap GR32:$src), addr:$dst)]>,
+                       EVEX, NoCD8, T_MAP4;
+  def MOVBE64mr_EVEX : RI<0x61, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
+                         "movbe{q}\t{$src, $dst|$dst, $src}",
+                         [(store (bswap GR64:$src), addr:$dst)]>,
+                       EVEX, NoCD8, T_MAP4;
+  }
+}
+
+let SchedRW = [WriteALU], Predicates = [HasMOVBE, HasNDD, In64BitMode] in {
+def MOVBE16rr_EVEX : I<0x61, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
+                        "movbe{w}\t{$src, $dst|$dst, $src}",
+                        [(set GR16:$dst, (bswap GR16:$src))]>,
+                      EVEX, NoCD8, T_MAP4, PD;
+def MOVBE32rr_EVEX : I<0x61, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
+                        "movbe{l}\t{$src, $dst|$dst, $src}",
+                        [(set GR32:$dst, (bswap GR32:$src))]>,
+                      EVEX, NoCD8, T_MAP4;
+def MOVBE64rr_EVEX : RI<0x61, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
+                        "movbe{q}\t{$src, $dst|$dst, $src}",
+                        [(set GR64:$dst, (bswap GR64:$src))]>,
+                      EVEX, NoCD8, T_MAP4;
+
+def MOVBE16rr_EVEX_REV : I<0x60, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
+                            "movbe{w}\t{$src, $dst|$dst, $src}", []>,
----------------
KanRobert wrote:

Reverse encoding should inherits class DisassemblyOnly.

And put the decoding tests at ./llvm/test/MC/Disassembler/X86/apx/reverse-encoding.txt

https://github.com/llvm/llvm-project/pull/77431