[llvm] [ARM] Add pass for handling undef early-clobber values (PR #77770)

[Jack Styles via llvm-commits]

Stylie777 wrote:

@tmatheson-arm to answer your question, the passes are similar to one another in some aspects and different in others. The logic employed is very similar, with how it checks for early-clobber and undef values. The differences come in how it applies the Pseudo instruction. For this solution with ARM, we have one instruction which takes on the form of a `ARM::MQPRRegClass` type. RISC V has multiple different ways of allocating the pseudo instructions, their version uses four different instructions that can be used depending on the situation.

That difference is my concern in making this a generic pass, and how it would deal with the different architectures and register configurations. 

https://github.com/llvm/llvm-project/pull/77770