[llvm] a946934 - [GlobalISel][NFC] Use GPhi wrapper in more places instead of iterating over operands.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 11 22:26:05 PST 2024
Author: Amara Emerson
Date: 2024-01-11T22:25:53-08:00
New Revision: a946934a122abae22ef4610acc26daf5891b4b72
URL: https://github.com/llvm/llvm-project/commit/a946934a122abae22ef4610acc26daf5891b4b72
DIFF: https://github.com/llvm/llvm-project/commit/a946934a122abae22ef4610acc26daf5891b4b72.diff
LOG: [GlobalISel][NFC] Use GPhi wrapper in more places instead of iterating over operands.
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
index 14885d5f9d08ee..4e110200c30a66 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -564,11 +564,11 @@ class GPhi : public GenericMachineInstr {
/// Returns the number of incoming values.
unsigned getNumIncomingValues() const { return (getNumOperands() - 1) / 2; }
/// Returns the I'th incoming vreg.
- Register getIncomingValue(unsigned I) {
+ Register getIncomingValue(unsigned I) const {
return getOperand(I * 2 + 1).getReg();
}
/// Returns the I'th incoming basic block.
- MachineBasicBlock *getIncomingBlock(unsigned I) {
+ MachineBasicBlock *getIncomingBlock(unsigned I) const {
return getOperand(I * 2 + 2).getMBB();
}
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 866774bda3fb14..ca5496476e86d8 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -3874,9 +3874,8 @@ bool CombinerHelper::matchLoadOrCombine(
bool CombinerHelper::matchExtendThroughPhis(MachineInstr &MI,
MachineInstr *&ExtMI) {
- assert(MI.getOpcode() == TargetOpcode::G_PHI);
-
- Register DstReg = MI.getOperand(0).getReg();
+ auto &PHI = cast<GPhi>(MI);
+ Register DstReg = PHI.getReg(0);
// TODO: Extending a vector may be expensive, don't do this until heuristics
// are better.
@@ -3905,8 +3904,8 @@ bool CombinerHelper::matchExtendThroughPhis(MachineInstr &MI,
// they'll be optimized in some way.
// Collect the unique incoming values.
SmallPtrSet<MachineInstr *, 4> InSrcs;
- for (unsigned Idx = 1; Idx < MI.getNumOperands(); Idx += 2) {
- auto *DefMI = getDefIgnoringCopies(MI.getOperand(Idx).getReg(), MRI);
+ for (unsigned I = 0; I < PHI.getNumIncomingValues(); ++I) {
+ auto *DefMI = getDefIgnoringCopies(PHI.getIncomingValue(I), MRI);
switch (DefMI->getOpcode()) {
case TargetOpcode::G_LOAD:
case TargetOpcode::G_TRUNC:
@@ -3914,7 +3913,7 @@ bool CombinerHelper::matchExtendThroughPhis(MachineInstr &MI,
case TargetOpcode::G_ZEXT:
case TargetOpcode::G_ANYEXT:
case TargetOpcode::G_CONSTANT:
- InSrcs.insert(getDefIgnoringCopies(MI.getOperand(Idx).getReg(), MRI));
+ InSrcs.insert(DefMI);
// Don't try to propagate if there are too many places to create new
// extends, chances are it'll increase code size.
if (InSrcs.size() > 2)
@@ -3929,7 +3928,7 @@ bool CombinerHelper::matchExtendThroughPhis(MachineInstr &MI,
void CombinerHelper::applyExtendThroughPhis(MachineInstr &MI,
MachineInstr *&ExtMI) {
- assert(MI.getOpcode() == TargetOpcode::G_PHI);
+ auto &PHI = cast<GPhi>(MI);
Register DstReg = ExtMI->getOperand(0).getReg();
LLT ExtTy = MRI.getType(DstReg);
@@ -3938,8 +3937,8 @@ void CombinerHelper::applyExtendThroughPhis(MachineInstr &MI,
// deterministic iteration order.
SmallSetVector<MachineInstr *, 8> SrcMIs;
SmallDenseMap<MachineInstr *, MachineInstr *, 8> OldToNewSrcMap;
- for (unsigned SrcIdx = 1; SrcIdx < MI.getNumOperands(); SrcIdx += 2) {
- auto SrcReg = MI.getOperand(SrcIdx).getReg();
+ for (unsigned I = 0; I < PHI.getNumIncomingValues(); ++I) {
+ auto SrcReg = PHI.getIncomingValue(I);
auto *SrcMI = MRI.getVRegDef(SrcReg);
if (!SrcMIs.insert(SrcMI))
continue;
@@ -3952,8 +3951,7 @@ void CombinerHelper::applyExtendThroughPhis(MachineInstr &MI,
Builder.setInsertPt(*SrcMI->getParent(), InsertPt);
Builder.setDebugLoc(MI.getDebugLoc());
- auto NewExt = Builder.buildExtOrTrunc(ExtMI->getOpcode(), ExtTy,
- SrcReg);
+ auto NewExt = Builder.buildExtOrTrunc(ExtMI->getOpcode(), ExtTy, SrcReg);
OldToNewSrcMap[SrcMI] = NewExt;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 391c2b9ec256ea..d42496ef09ee8f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3765,16 +3765,16 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
// properly.
//
// TODO: There are additional exec masking dependencies to analyze.
- if (MI.getOpcode() == TargetOpcode::G_PHI) {
+ if (auto *PHI = dyn_cast<GPhi>(&MI)) {
unsigned ResultBank = AMDGPU::InvalidRegBankID;
- Register DstReg = MI.getOperand(0).getReg();
+ Register DstReg = PHI->getReg(0);
// Sometimes the result may have already been assigned a bank.
if (const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI))
ResultBank = DstBank->getID();
- for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
- Register Reg = MI.getOperand(I).getReg();
+ for (unsigned I = 0; I < PHI->getNumIncomingValues(); ++I) {
+ Register Reg = PHI->getIncomingValue(I);
const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
// FIXME: Assuming VGPR for any undetermined inputs.
diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
index b38ca3f09ffbe2..db7afc3c86c57e 100644
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -238,11 +238,11 @@ MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer(
if (MI->getOpcode() == TargetOpcode::G_STORE)
addUseDef(MI->getOperand(0).getReg(), MRI);
- if (MI->getOpcode() == TargetOpcode::G_PHI) {
- addDefUses(MI->getOperand(0).getReg(), MRI);
+ if (auto *PHI = dyn_cast<GPhi>(MI)) {
+ addDefUses(PHI->getReg(0), MRI);
- for (unsigned i = 1; i < MI->getNumOperands(); i += 2)
- addUseDef(MI->getOperand(i).getReg(), MRI);
+ for (unsigned I = 1; I < PHI->getNumIncomingValues(); ++I)
+ addUseDef(PHI->getIncomingValue(I), MRI);
}
if (MI->getOpcode() == TargetOpcode::G_SELECT) {
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