[llvm] [RISCV] Simplify the description for ssaia and smaia. (PR #77870)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 11 19:51:10 PST 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/77870
It feels more important to expand out Advanced Interrupt Architecture for users than to have a description that explains how one extension is different from the other.
>From 771c1897b11916e40ff4e05337f2265c30f1a506 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 11 Jan 2024 19:49:05 -0800
Subject: [PATCH] [RISCV] Simplify the description for ssaia and smaia.
It feels more important to expand out Advanced Interrupt Architecture
for users than to have a description that explains how one extension is
different from the other.
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 4c99d8ce61ef02..72b9c2cade62c7 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -711,16 +711,13 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
def FeatureStdExtSmaia
: SubtargetFeature<"smaia", "HasStdExtSmaia", "true",
- "'Smaia' (Smaia encompasses all added CSRs and all "
- "modifications to interrupt response behavior that the "
- "AIA specifies for a hart, over all privilege levels.)",
- []>;
+ "'Smaia' (Advanced Interrupt Architecture Machine "
+ "Level)", []>;
def FeatureStdExtSsaia
: SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
- "'Ssaia' (Ssaia is essentially the same as Smaia except "
- "excluding the machine-level CSRs and behavior not "
- "directly visible to supervisor level.)", []>;
+ "'Ssaia' (Advanced Interrupt Architecture Supervisor "
+ "Level)", []>;
def HasHalfFPLoadStoreMove
: Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
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