[llvm] [AMDGPU] Prefer lower total register usage in regions with spilling (PR #71882)

[Jeffrey Byrnes via llvm-commits]

jrbyrnes wrote:

> This part doesn't entirely make sense to me. The SGPR spill code may end up larger, but could still be faster. Unless the spill-to-vgpr handling ends up inducing a VGPR spill, I'd spill expect to prefer an excess SGPR to excess VGPR

Okay, I have modified it to reflect the principle: prefer the register pressure with SGPR-spills-to-VGPR when there is a tie in Excess VGPR pressure.

That the following behavior is observed:


|Case		|Pressure 1		|Pressure 2			|Winner     |
|-----------|---------------|-------------------|-----------|
|0			|(2,0)			|(1,1)				|Pressure 2 |
|1 			|(1,1)			|(1,63)				|Pressure 1 |
|2 			|(2,0)			|(1,63)				|Pressure 2 |
|3			|(2,0)			|(1,64)				|Pressure 2 |
|4			|(3,0)			|(1,64)				|Pressure 2 |
|5			|(3,0)			|(1,128)			|Pressure 2 |
|6			|(3,0)			|(0,1280)*			|Pressure 2 |


It also has the following behvaior: 

|Case		|Pressure 1		|Pressure 2			|Winner     |
|-----------|---------------|-------------------|-----------|
|7			|(0,0)			|(0,1)*				|Pressure 1 |


*VGPR usage is not excess even with VGPR usage from SGPR spills.






https://github.com/llvm/llvm-project/pull/71882