[llvm] [WIP][GISel][RISCV] Implement selectShiftMask. (PR #77572)

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git-clang-format --diff 52d1397e38ee88b170585c9c824d08e6975890ca b22fe66d5a72bfb3f552dbe861cc5ad5a608c422 -- llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 705bfd8869..fee1305667 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -201,31 +201,23 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const {
       // If we are shifting by N-X where N == 0 mod Size, then just shift by -X
       // to generate a NEG instead of a SUB of a constant.
       ShAmtReg = MRI.createGenericVirtualRegister(ShiftLLT);
-      unsigned NegOpc = Subtarget->is64Bit()? RISCV::SUBW : RISCV::SUB;
-      return {
-        {
-          [=](MachineInstrBuilder &MIB) { 
-            MachineIRBuilder(*MIB.getInstr())
+      unsigned NegOpc = Subtarget->is64Bit() ? RISCV::SUBW : RISCV::SUB;
+      return {{[=](MachineInstrBuilder &MIB) {
+        MachineIRBuilder(*MIB.getInstr())
             .buildInstr(NegOpc, {ShAmtReg}, {Register(RISCV::X0), Reg});
-            MIB.addReg(ShAmtReg);
-          }
-        }
-      };
+        MIB.addReg(ShAmtReg);
+      }}};
     }
     if ((Imm.urem(ShiftWidth) & (ShiftWidth - 1)) == ShiftWidth - 1) {
-    // If we are shifting by N-X where N == -1 mod Size, then just shift by ~X
-    // to generate a NOT instead of a SUB of a constant.
+      // If we are shifting by N-X where N == -1 mod Size, then just shift by ~X
+      // to generate a NOT instead of a SUB of a constant.
       ShAmtReg = MRI.createGenericVirtualRegister(ShiftLLT);
-      return {
-        {
-          [=](MachineInstrBuilder &MIB) { 
-            MachineIRBuilder(*MIB.getInstr())
+      return {{[=](MachineInstrBuilder &MIB) {
+        MachineIRBuilder(*MIB.getInstr())
             .buildInstr(RISCV::XORI, {ShAmtReg}, {Reg})
             .addImm(-1);
-            MIB.addReg(ShAmtReg);
-          }
-        }
-      };
+        MIB.addReg(ShAmtReg);
+      }}};
     }
   }
 

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https://github.com/llvm/llvm-project/pull/77572