[llvm] [AArch64] Fix missing `pfalse` diagnostic (PR #77746)
Momchil Velikov via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 11 08:04:11 PST 2024
https://github.com/momchil-velikov updated https://github.com/llvm/llvm-project/pull/77746
>From 7d0582c23947669b6054b41a0ba5b0da34bb4af6 Mon Sep 17 00:00:00 2001
From: Momchil Velikov <momchil.velikov at arm.com>
Date: Wed, 10 Jan 2024 18:32:49 +0000
Subject: [PATCH] [AArch64] Fix missing `pfalse` diagnostic
The missing diagnostic causes a ICE when a suffix other than `.B`
is used in a `pfalse` instruction with a predicate-as-counter operand.
---
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 4 ++++
llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s | 5 +++++
2 files changed, 9 insertions(+)
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index be66790c427767..f6ea262d69e4d5 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6110,6 +6110,9 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
case Match_AddSubLSLImm3ShiftLarge:
return Error(Loc,
"expected 'lsl' with optional integer in range [0, 7]");
+ case Match_InvalidSVEPNRasPPRPredicateBReg:
+ return Error(Loc,
+ "Expected predicate-as-counter register name with .B suffix");
default:
llvm_unreachable("unexpected error code!");
}
@@ -6690,6 +6693,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidSVEVectorListStrided4x16:
case Match_InvalidSVEVectorListStrided4x32:
case Match_InvalidSVEVectorListStrided4x64:
+ case Match_InvalidSVEPNRasPPRPredicateBReg:
case Match_MSR:
case Match_MRS: {
if (ErrorInfo >= Operands.size())
diff --git a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
index 4f2c22c4a88895..f4d95c5910d895 100644
--- a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
@@ -15,3 +15,8 @@ pfalse pn16.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: pfalse pn16.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pfalse pn5.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Expected predicate-as-counter register name with .B suffix
+// CHECK-NEXT: pfalse pn5.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
More information about the llvm-commits
mailing list