[llvm] [PowerPC] Fix shuffle combine with undef elements (PR #77787)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 11 07:47:40 PST 2024
https://github.com/nikic created https://github.com/llvm/llvm-project/pull/77787
This custom DAG combine works on a shuffle where one source vector is a zero splat, which means we can adjust the shuffle indices to refer to any element of the splat -- as long as we stay in the same vector.
In the case where an undef (-1) index into the non-splat vector was used, we ended up adjusting the splat index to -1+NumElements, which points into the wrong vector.
Fix this by not adjusting indices where the other one is undef. There are four cases this theoretically affects, but in practice I only mangaged to demonstrate a miscompile with one of them. I think two of theses are effectively dead due to the operand canonicalization at the start of the transform.
Fixes https://github.com/llvm/llvm-project/issues/77748.
>From 296ed0bbb6972d5f2480d9f207b56249a6e5ea39 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Thu, 11 Jan 2024 15:36:40 +0100
Subject: [PATCH] [PowerPC] Fix shuffle combine with undef elements
This custom DAG combine works on a shuffle where one source vector
is a zero splat, which means we can adjust the shuffle indices to
refer to any element of the splat -- as long as we stay in the same
vector.
In the case where an undef (-1) index into the non-splat vector was
used, we ended up adjusting the splat index to -1+NumElements,
which points into the wrong vector.
Fix this by not adjusting indices where the other one is undef.
There are four cases this theoretically affects, but in practice
I only mangaged to demonstrate a miscompile with one of them.
I think two of theses are effectively dead due to the operand
canonicalization at the start of the transform.
Fixes https://github.com/llvm/llvm-project/issues/77748.
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 8 ++++----
llvm/test/CodeGen/PowerPC/pr77748.ll | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 4e164fda1d8dd8..743f6493f02215 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15428,7 +15428,7 @@ SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN,
// vector_shuffle<0,16,1,17,2,18,3,19,4,20,5,21,6,22,7,23> t1, <zero>
if (Mask[0] < NumElts)
for (int i = 1, e = Mask.size(); i < e; i += 2) {
- if (ShuffV[i] < 0)
+ if (ShuffV[i] < 0 || ShuffV[i - 1] < 0)
continue;
ShuffV[i] = (ShuffV[i - 1] + NumElts);
}
@@ -15436,7 +15436,7 @@ SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN,
// vector_shuffle<16,0,17,1,18,2,19,3,20,4,21,5,22,6,23,7> t1, <zero>
else
for (int i = 0, e = Mask.size(); i < e; i += 2) {
- if (ShuffV[i] < 0)
+ if (ShuffV[i] < 0 || ShuffV[i + 1] < 0)
continue;
ShuffV[i] = (ShuffV[i + 1] + NumElts);
}
@@ -15445,7 +15445,7 @@ SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN,
// vector_shuffle<0,16,1,17,2,18,3,19,4,20,5,21,6,22,7,23> <zero>, t1
if (Mask[0] < NumElts)
for (int i = 0, e = Mask.size(); i < e; i += 2) {
- if (ShuffV[i] < 0)
+ if (ShuffV[i] < 0 || ShuffV[i + 1] < 0)
continue;
ShuffV[i] = ShuffV[i + 1] - NumElts;
}
@@ -15453,7 +15453,7 @@ SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN,
// vector_shuffle<16,0,17,1,18,2,19,3,20,4,21,5,22,6,23,7> <zero>, t1
else
for (int i = 1, e = Mask.size(); i < e; i += 2) {
- if (ShuffV[i] < 0)
+ if (ShuffV[i] < 0 || ShuffV[i - 1] < 0)
continue;
ShuffV[i] = ShuffV[i - 1] - NumElts;
}
diff --git a/llvm/test/CodeGen/PowerPC/pr77748.ll b/llvm/test/CodeGen/PowerPC/pr77748.ll
index 661ea29445a891..7ec721def0093b 100644
--- a/llvm/test/CodeGen/PowerPC/pr77748.ll
+++ b/llvm/test/CodeGen/PowerPC/pr77748.ll
@@ -14,13 +14,13 @@
; LE-NEXT: .byte 28
; LE-NEXT: .byte 12
; LE-NEXT: .byte 31
-; LE-NEXT: .byte 16
+; LE-NEXT: .byte 15
; LE-NEXT: .byte 31
-; LE-NEXT: .byte 16
+; LE-NEXT: .byte 15
; LE-NEXT: .byte 31
-; LE-NEXT: .byte 16
+; LE-NEXT: .byte 15
; LE-NEXT: .byte 31
-; LE-NEXT: .byte 16
+; LE-NEXT: .byte 15
; BE-LABEL: .LCPI0_0:
; BE-NEXT: .byte 0
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