[llvm] [Aarch64] Add missing earlyclobber to sqrshr and uqrshl instructions. (PR #77782)

[via llvm-commits]

github-actions[bot] wrote:

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:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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git-clang-format --diff ef4a95c86210e11cf4bfbf545c2f859b5c772888 b7a540e215e61cd2b9cf8e7e5f2889daae55d65f -- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 7414b5307f..f666c028b9 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8311,8 +8311,8 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
   case ARM::MVE_SQRSHR:
   case ARM::MVE_UQRSHL: {
     if (Operands[2]->getReg() == Operands[3]->getReg()) {
-      return Error (Operands[2]->getStartLoc(),
-                    "Rda register and Rm register can't be identical");
+      return Error(Operands[2]->getStartLoc(),
+                   "Rda register and Rm register can't be identical");
     }
     break;
   }

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https://github.com/llvm/llvm-project/pull/77782