[llvm] [AArch64][SME2] Add ZT0 attributes to SMEAttrs (PR #77607)

[Sander de Smalen via llvm-commits]

================
@@ -29,14 +29,19 @@ class SMEAttrs {
   // Enum with bitmasks for each individual SME feature.
   enum Mask {
     Normal = 0,
-    SM_Enabled = 1 << 0,    // aarch64_pstate_sm_enabled
-    SM_Compatible = 1 << 1, // aarch64_pstate_sm_compatible
-    SM_Body = 1 << 2,       // aarch64_pstate_sm_body
-    ZA_Shared = 1 << 3,     // aarch64_pstate_sm_shared
-    ZA_New = 1 << 4,        // aarch64_pstate_sm_new
-    ZA_Preserved = 1 << 5,  // aarch64_pstate_sm_preserved
-    ZA_NoLazySave = 1 << 6, // Used for SME ABI routines to avoid lazy saves
-    All = ZA_Preserved - 1
+    SM_Enabled = 1 << 0,     // aarch64_pstate_sm_enabled
+    SM_Compatible = 1 << 1,  // aarch64_pstate_sm_compatible
+    SM_Body = 1 << 2,        // aarch64_pstate_sm_body
+    ZA_Shared = 1 << 3,      // aarch64_pstate_sm_shared
+    ZA_New = 1 << 4,         // aarch64_pstate_sm_new
+    ZA_Preserved = 1 << 5,   // aarch64_pstate_sm_preserved
+    ZA_NoLazySave = 1 << 6,  // Used for SME ABI routines to avoid lazy saves
+    ZT0_New = 1 << 7,        // aarch64_sme_zt0_new
+    ZT0_In = 1 << 8,         // aarch64_sme_zt0_in
+    ZT0_Out = 1 << 9,        // aarch64_sme_zt0_out
+    ZT0_InOut = 1 << 10,     // aarch64_sme_zt0_inout
+    ZT0_Preserved = 1 << 11, // aarch64_sme_zt0_preserved
----------------
sdesmalen-arm wrote:

Given that they are all mutually exclusive, you could reserve a few bits to represent that state, i.e.
```
enum class StateValue {
  None = 0,
  In = 1,
  Out = 2,
  InOut = 3,
  Preserved = 4,
  New = 5
};
```
with the bits in `enum Mask` being:
```
  ZT0_Shift = 7,
  ZT0_Mask = 0b111 << ZT0_Shift,
```

To get/set the SMEState value, you'd do something like this:
```
  StateValue getZT0State() const { return BitMask & ZT0_Mask >> ZT0_Shift; }
  void setZT0State(StateValue S) { BitMask |= S << ZT0_Shift; }
```
(possibly with some added casts)

https://github.com/llvm/llvm-project/pull/77607