[llvm] [AArch64] Fix missing `pfalse` diagnostic (PR #77746)

Momchil Velikov via llvm-commits llvm-commits at lists.llvm.org
Thu Jan 11 02:22:11 PST 2024 

https://github.com/momchil-velikov created https://github.com/llvm/llvm-project/pull/77746

The missing diagnostic causes a ICE when a suffix other than `.B`
is used in a `pfalse` instruction with a predicate-as-counter operand

>From 58fc2df63c567bccf462cd6b0c364492b105dc00 Mon Sep 17 00:00:00 2001
From: Momchil Velikov <momchil.velikov at arm.com>
Date: Wed, 10 Jan 2024 17:56:09 +0000
Subject: [PATCH 1/2] [AArch64] Enable certain instruction aliases for SVE/SME

Several SVE instruction aliases accept predicate-as-counter register
names as a convenience. These ought to be enabled with SVE/SME
because the underlying encoding is valid and it's required by Arm ARM.
---
 .../lib/Target/AArch64/AArch64SVEInstrInfo.td |  4 +++-
 .../SVE/predicate-as-counter-aliases.s        | 22 +++++++++----------
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 26102f922d99fe..4782ad076c605d 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -4006,7 +4006,9 @@ defm WHILEHS_CXX  : sve2p1_int_while_rr_pn<"whilehs", 0b100>;
 defm WHILEHI_CXX  : sve2p1_int_while_rr_pn<"whilehi", 0b101>;
 defm WHILELO_CXX  : sve2p1_int_while_rr_pn<"whilelo", 0b110>;
 defm WHILELS_CXX  : sve2p1_int_while_rr_pn<"whilels", 0b111>;
+} // End HasSVE2p1_or_HasSME2
 
+let Predicates = [HasSVEorSME] in {
 
 // Aliases for existing SVE instructions for which predicate-as-counter are
 // accepted as an operand to the instruction
@@ -4025,7 +4027,7 @@ def : InstAlias<"mov $Pd, $Pn",
 
 def : InstAlias<"pfalse\t$Pd", (PFALSE PNRasPPR8:$Pd), 0>;
 
-} // End HasSVE2p1_or_HasSME2
+}
 
 //===----------------------------------------------------------------------===//
 // Non-widening BFloat16 to BFloat16 instructions
diff --git a/llvm/test/MC/AArch64/SVE/predicate-as-counter-aliases.s b/llvm/test/MC/AArch64/SVE/predicate-as-counter-aliases.s
index bca2cf913ff64a..fd6c59888e097d 100644
--- a/llvm/test/MC/AArch64/SVE/predicate-as-counter-aliases.s
+++ b/llvm/test/MC/AArch64/SVE/predicate-as-counter-aliases.s
@@ -1,50 +1,50 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
-// RUN:        | llvm-objdump --no-print-imm-hex -d --mattr=+sve2p1 - | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 
 ldr     pn0, [x0]
 // CHECK-INST: ldr     p0, [x0]
 // CHECK-ENCODING: [0x00,0x00,0x80,0x85]
-// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 85800000 <unknown>
 
 ldr     pn5, [x10, #255, mul vl]
 // CHECK-INST: ldr     p5, [x10, #255, mul vl]
 // CHECK-ENCODING: [0x45,0x1d,0x9f,0x85]
-// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 859f1d45 <unknown>
 
 
 str     pn0, [x0]
 // CHECK-INST: str     p0, [x0]
 // CHECK-ENCODING: [0x00,0x00,0x80,0xe5]
-// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5800000 <unknown>
 
 str     pn5, [x10, #255, mul vl]
 // CHECK-INST: str     p5, [x10, #255, mul vl]
 // CHECK-ENCODING: [0x45,0x1d,0x9f,0xe5]
-// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e59f1d45 <unknown>
 
 
 mov     pn0.b, pn0.b
 // CHECK-INST: mov     p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x80,0x25]
-// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 25804000 <unknown>
 
 
 pfalse pn15.b
 // CHECK-INST: pfalse  p15.b
 // CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
-// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 2518e40f <unknown>

>From 9842764b9522cca9d02e66f2bad48727bbf85bad Mon Sep 17 00:00:00 2001
From: Momchil Velikov <momchil.velikov at arm.com>
Date: Wed, 10 Jan 2024 18:32:49 +0000
Subject: [PATCH 2/2] [AArch64] Fix missing `pfalse` diagnostic

The missing diagnostic causes a ICE when a suffix other than `.B`
is used in a `pfalse` instruction with a predicate-as-counter operand.
---
 llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 4 ++++
 llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s          | 5 +++++
 2 files changed, 9 insertions(+)

diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index be66790c427767..f6ea262d69e4d5 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6110,6 +6110,9 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_AddSubLSLImm3ShiftLarge:
     return Error(Loc,
       "expected 'lsl' with optional integer in range [0, 7]");
+  case Match_InvalidSVEPNRasPPRPredicateBReg:
+    return Error(Loc,
+                 "Expected predicate-as-counter register name with .B suffix");
   default:
     llvm_unreachable("unexpected error code!");
   }
@@ -6690,6 +6693,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidSVEVectorListStrided4x16:
   case Match_InvalidSVEVectorListStrided4x32:
   case Match_InvalidSVEVectorListStrided4x64:
+  case Match_InvalidSVEPNRasPPRPredicateBReg:
   case Match_MSR:
   case Match_MRS: {
     if (ErrorInfo >= Operands.size())
diff --git a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
index 4f2c22c4a88895..f4d95c5910d895 100644
--- a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
@@ -15,3 +15,8 @@ pfalse pn16.b
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: pfalse pn16.b
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pfalse pn5.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Expected predicate-as-counter register name with .B suffix
+// CHECK-NEXT: pfalse pn5.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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