[llvm] [X86][CodeGen] Support EVEX compression: NDD to nonNDD (PR #77731)

[Shengchen Kan via llvm-commits]

================
@@ -241,26 +264,37 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
   //
   // For AVX512 cases, EVEX prefix is needed in order to carry this information
   // thus preventing the transformation to VEX encoding.
-  if (TSFlags & X86II::EVEX_B)
+  bool IsND = X86II::hasNewDataDest(TSFlags);
+  if (TSFlags & X86II::EVEX_B && !IsND)
+    return false;
+
+  if (IsND && !isRedundantNewDataDest(MI, ST))
     return false;
 
   ArrayRef<X86CompressEVEXTableEntry> Table = ArrayRef(X86CompressEVEXTable);
 
   unsigned Opc = MI.getOpcode();
   const auto *I = llvm::lower_bound(Table, Opc);
-  if (I == Table.end() || I->OldOpc != Opc)
+  if (I == Table.end() || I->OldOpc != Opc) {
+    assert(!IsND && "Missing entry for ND instruction");
     return false;
+  }
 
-  if (usesExtendedRegister(MI) || !checkVEXInstPredicate(Opc, ST) ||
-      !performCustomAdjustments(MI, I->NewOpc))
-    return false;
+  if (!IsND) {
+    if (usesExtendedRegister(MI) || !checkVEXInstPredicate(Opc, ST) ||
+        !performCustomAdjustments(MI, I->NewOpc))
+      return false;
+  }
 
   const MCInstrDesc &NewDesc = ST.getInstrInfo()->get(I->NewOpc);
   MI.setDesc(NewDesc);
   uint64_t Encoding = NewDesc.TSFlags & X86II::EncodingMask;
   auto AsmComment =
       (Encoding == X86II::VEX) ? X86::AC_EVEX_2_VEX : X86::AC_EVEX_2_LEGACY;
   MI.setAsmPrinterFlag(AsmComment);
+  if (IsND)
----------------
KanRobert wrote:

No, `IsND` can be false here.

https://github.com/llvm/llvm-project/pull/77731