[llvm] [MacroFusion][RISCV] Allocate same register for second instruction of fusible pair (PR #77461)

[Wang Pengcheng via llvm-commits]

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@@ -114,6 +114,7 @@ class MachineInstr
                              // this instruction.
     Unpredictable = 1 << 16, // Instruction with unpredictable condition.
     NoConvergent = 1 << 17,  // Call does not require convergence guarantees.
+    Fusible = 1 << 18,       // Instruction is the second of a fusible pair.
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wangpc-pp wrote:

> What if the second fusion instruction is an instruction with 2 register sources

Currently, I think this is a uncommon case and I don't know if there are such fusions. Do you have any example? Maybe integer multiply-add fusion?
Even if so, I think we can know the constrainted operands via its opcode and constrain them in the `getRegAllocationHints` implementation. We don't need to record this info in target-independent part.

https://github.com/llvm/llvm-project/pull/77461