[llvm] [AMDGPU][MC] Fix the ABS, NEG, and OMOD bits in V_PERMLANE instruction encoding (PR #77713)

[Shilei Tian via llvm-commits]

https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/77713

Per the reference guide, the ABS, NEG, and OMOD bits need to be zero.

Fix #59547.


>From 33fd1eac99a97563cae6a49cfd177151536e0b75 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Wed, 10 Jan 2024 20:17:57 -0500
Subject: [PATCH] [AMDGPU][MC] Fix the ABS, NEG, and OMOD bits in V_PERMLANE
 instruction encoding

Per the reference guide, the ABS, NEG, and OMOD bits need to be zero.

Fix #59547.
---
 llvm/lib/Target/AMDGPU/VOP3Instructions.td |  4 +++
 llvm/test/MC/AMDGPU/gfx11_asm_permlane.s   | 37 ++++++++++++++++++++++
 2 files changed, 41 insertions(+)
 create mode 100644 llvm/test/MC/AMDGPU/gfx11_asm_permlane.s

diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index eebd323210f95f..ed0120acd3e4f2 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -733,6 +733,10 @@ def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3
   let HasClamp = 0;
   let HasExtVOP3DPP = 0;
   let HasExtDPP = 0;
+  let HasSrc0Mods = 0;
+  let HasSrc1Mods = 0;
+  let HasSrc2Mods = 0;
+  let HasOMod = 0;
 }
 
 def VOP3_PERMLANE_VAR_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, untyped]>, VOP3_OPSEL> {
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_permlane.s b/llvm/test/MC/AMDGPU/gfx11_asm_permlane.s
new file mode 100644
index 00000000000000..b53e229481dce3
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_permlane.s
@@ -0,0 +1,37 @@
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s
+
+; CHECK: encoding: [0x00,0x08,0x5b,0xd6,0x00,0x0f,0x00,0x00]
+v_permlane16_b32 v0, v0, s7, s0 op_sel:[1,0]
+
+; CHECK: encoding: [0x00,0x10,0x5b,0xd6,0x00,0x0f,0x00,0x00]
+v_permlane16_b32 v0, v0, s7, s0 op_sel:[0,1]
+
+; CHECK: encoding: [0x00,0x18,0x5b,0xd6,0x00,0x0f,0x00,0x00]
+v_permlane16_b32 v0, v0, s7, s0 op_sel:[1,1]
+
+; CHECK: encoding: [0x00,0x08,0x5c,0xd6,0x00,0x0f,0x00,0x00]
+v_permlanex16_b32 v0, v0, s7, s0 op_sel:[1,0]
+
+; CHECK: encoding: [0x00,0x10,0x5c,0xd6,0x00,0x0f,0x00,0x00]
+v_permlanex16_b32 v0, v0, s7, s0 op_sel:[0,1]
+
+; CHECK: encoding: [0x00,0x18,0x5c,0xd6,0x00,0x0f,0x00,0x00]
+v_permlanex16_b32 v0, v0, s7, s0 op_sel:[1,1]
+
+; CHECK: encoding: [0x00,0x08,0x5b,0xd6,0x00,0x05,0x0c,0x00]
+v_permlane16_b32 v0, v0, s2, s3 op_sel:[1,0]
+
+; CHECK: encoding: [0x00,0x10,0x5b,0xd6,0x00,0x05,0x0c,0x00]
+v_permlane16_b32 v0, v0, s2, s3 op_sel:[0,1]
+
+; CHECK: encoding: [0x00,0x18,0x5b,0xd6,0x00,0x05,0x0c,0x00]
+v_permlane16_b32 v0, v0, s2, s3 op_sel:[1,1]
+
+; CHECK: encoding: [0x00,0x08,0x5c,0xd6,0x00,0x05,0x0c,0x00]
+v_permlanex16_b32 v0, v0, s2, s3 op_sel:[1,0]
+
+; CHECK: encoding: [0x00,0x10,0x5c,0xd6,0x00,0x05,0x0c,0x00]
+v_permlanex16_b32 v0, v0, s2, s3 op_sel:[0,1]
+
+; CHECK: encoding: [0x00,0x18,0x5c,0xd6,0x00,0x05,0x0c,0x00]
+v_permlanex16_b32 v0, v0, s2, s3 op_sel:[1,1]