[llvm] 03be448 - [RISCV][AMDGPU] Mark test/CodeGen/Generic/live-debug-label.ll XFAIL for RISCV and AMDGPU (#77631)

[via llvm-commits]

Author: Min-Yih Hsu
Date: 2024-01-10T16:47:34-08:00
New Revision: 03be448cce8b6a5f1aa36fc1b316508b08b3aa9f

URL: https://github.com/llvm/llvm-project/commit/03be448cce8b6a5f1aa36fc1b316508b08b3aa9f
DIFF: https://github.com/llvm/llvm-project/commit/03be448cce8b6a5f1aa36fc1b316508b08b3aa9f.diff

LOG: [RISCV][AMDGPU] Mark test/CodeGen/Generic/live-debug-label.ll XFAIL for RISCV and AMDGPU (#77631)

Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen
pipeline. This test prematurely stops at the first one, which doesn't
cleanup the virtual register map and cause an assertion failure. Ideally
we can solve this by teaching `-stop-after` how to stop at the last
instance of a Pass, but we're just marking XFAIL for these two targets
for now.

Added: 
    

Modified: 
    llvm/test/CodeGen/Generic/live-debug-label.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/Generic/live-debug-label.ll b/llvm/test/CodeGen/Generic/live-debug-label.ll
index 5022e1f187d19f..3121b8700ed119 100644
--- a/llvm/test/CodeGen/Generic/live-debug-label.ll
+++ b/llvm/test/CodeGen/Generic/live-debug-label.ll
@@ -2,6 +2,13 @@
 ;
 ; NVPTX produces a 
diff erent order of the BBs
 ; XFAIL: target=nvptx{{.*}}
+; Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen
+; pipeline. This test prematurely stops at the first one, which doesn't cleanup
+; the virtual register map and cause an assertion failure. Ideally we can solve
+; this by teaching `-stop-after` how to stop at the last instance of a Pass,
+; but we're just marking XFAIL for these two targets for now.
+; XFAIL: target=riscv{{.*}}
+; XFAIL: target=amdgcn-{{.*}}
 
 ; Generated with "clang++ -g -O1 -S -emit-llvm"
 ;