[llvm] 0a1b066 - [RISCV] Support isel for Zacas for XLen and i32. (#77666)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 10 12:00:44 PST 2024
Author: Craig Topper
Date: 2024-01-10T12:00:40-08:00
New Revision: 0a1b066bbaf7e3800f47697231d7e1e91744ecbf
URL: https://github.com/llvm/llvm-project/commit/0a1b066bbaf7e3800f47697231d7e1e91744ecbf
DIFF: https://github.com/llvm/llvm-project/commit/0a1b066bbaf7e3800f47697231d7e1e91744ecbf.diff
LOG: [RISCV] Support isel for Zacas for XLen and i32. (#77666)
This adds new isel patterns for Zacas that take priority over the
pseudoinstructions we use for the A extension.
Support for 2x XLen types will come in a separate patch since they need
to be done differently.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoA.td
llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index bb7a3291085d43..279509575bb52a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -736,6 +736,7 @@ def FeatureStdExtZacas
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
AssemblerPredicate<(all_of FeatureStdExtZacas),
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
+def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
//===----------------------------------------------------------------------===//
// Vendor extensions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index 1ff5189260a9c7..44552c00c62e55 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -333,11 +333,17 @@ multiclass PseudoCmpXchgPat<string Op, Pseudo CmpXchgInst,
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 7)>;
}
-let Predicates = [HasStdExtA] in {
-
+let Predicates = [HasStdExtA, NoStdExtZacas] in {
def PseudoCmpXchg32 : PseudoCmpXchg;
defm : PseudoCmpXchgPat<"atomic_cmp_swap_32", PseudoCmpXchg32>;
+}
+
+let Predicates = [HasStdExtA, NoStdExtZacas, IsRV64] in {
+def PseudoCmpXchg64 : PseudoCmpXchg;
+defm : PseudoCmpXchgPat<"atomic_cmp_swap_64", PseudoCmpXchg64, i64>;
+}
+let Predicates = [HasStdExtA] in {
def PseudoMaskedCmpXchg32
: Pseudo<(outs GPR:$res, GPR:$scratch),
(ins GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask,
@@ -356,10 +362,6 @@ def : Pat<(int_riscv_masked_cmpxchg_i32
} // Predicates = [HasStdExtA]
let Predicates = [HasStdExtA, IsRV64] in {
-
-def PseudoCmpXchg64 : PseudoCmpXchg;
-defm : PseudoCmpXchgPat<"atomic_cmp_swap_64", PseudoCmpXchg64, i64>;
-
def : Pat<(int_riscv_masked_cmpxchg_i64
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering),
(PseudoMaskedCmpXchg32
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
index ea8046d119d042..ffcdd001074938 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
@@ -67,6 +67,57 @@ defm AMOCAS_D_RV64 : AMO_cas_aq_rl<0b00101, 0b011, "amocas.d", GPR>;
defm AMOCAS_Q : AMO_cas_aq_rl<0b00101, 0b100, "amocas.q", GPRPairRV64>;
} // Predicates = [HasStdExtZacas, IsRV64]
+multiclass AMOCASPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
+ list<Predicate> ExtraPreds = []> {
+ let Predicates = !listconcat([HasStdExtZacas, NotHasStdExtZtso], ExtraPreds) in {
+ def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (vt GPR:$addr),
+ (vt GPR:$cmp),
+ (vt GPR:$new)),
+ (!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
+ def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") (vt GPR:$addr),
+ (vt GPR:$cmp),
+ (vt GPR:$new)),
+ (!cast<RVInst>(BaseInst#"_AQ") GPR:$cmp, GPR:$addr, GPR:$new)>;
+ def : Pat<(!cast<PatFrag>(AtomicOp#"_release") (vt GPR:$addr),
+ (vt GPR:$cmp),
+ (vt GPR:$new)),
+ (!cast<RVInst>(BaseInst#"_RL") GPR:$cmp, GPR:$addr, GPR:$new)>;
+ def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") (vt GPR:$addr),
+ (vt GPR:$cmp),
+ (vt GPR:$new)),
+ (!cast<RVInst>(BaseInst#"_AQ_RL") GPR:$cmp, GPR:$addr, GPR:$new)>;
+ def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") (vt GPR:$addr),
+ (vt GPR:$cmp),
+ (vt GPR:$new)),
+ (!cast<RVInst>(BaseInst#"_AQ_RL") GPR:$cmp, GPR:$addr, GPR:$new)>;
+ } // Predicates = !listconcat([HasStdExtZacas, NotHasStdExtZtso], ExtraPreds)
+ let Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds) in {
+ def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (vt GPR:$addr),
+ (vt GPR:$cmp),
+ (vt GPR:$new)),
+ (!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
+ def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") (vt GPR:$addr),
+ (vt GPR:$cmp),
+ (vt GPR:$new)),
+ (!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
+ def : Pat<(!cast<PatFrag>(AtomicOp#"_release") (vt GPR:$addr),
+ (vt GPR:$cmp),
+ (vt GPR:$new)),
+ (!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
+ def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") (vt GPR:$addr),
+ (vt GPR:$cmp),
+ (vt GPR:$new)),
+ (!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
+ def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") (vt GPR:$addr),
+ (vt GPR:$cmp),
+ (vt GPR:$new)),
+ (!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
+ } // Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds)
+}
+
+defm : AMOCASPat<"atomic_cmp_swap_32", "AMOCAS_W">;
+defm : AMOCASPat<"atomic_cmp_swap_64", "AMOCAS_D_RV64", i64, [IsRV64]>;
+
//===----------------------------------------------------------------------===//
// Zawrs (Wait-on-Reservation-Set)
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
index 651f58d324422f..a8477cc550fe6a 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
@@ -1,30 +1,44 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=CHECK,RV32IA %s
+; RUN: | FileCheck -check-prefixes=NOZACAS,RV32IA %s
+; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=ZACAS,RV32IA-ZACAS %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=CHECK,RV64IA %s
+; RUN: | FileCheck -check-prefixes=NOZACAS,RV64IA %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=ZACAS,RV64IA-ZACAS %s
; Test cmpxchg followed by a branch on the cmpxchg success value to see if the
; branch is folded into the cmpxchg expansion.
define void @cmpxchg_and_branch1(ptr %ptr, i32 signext %cmp, i32 signext %val) nounwind {
-; CHECK-LABEL: cmpxchg_and_branch1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: .LBB0_1: # %do_cmpxchg
-; CHECK-NEXT: # =>This Loop Header: Depth=1
-; CHECK-NEXT: # Child Loop BB0_3 Depth 2
-; CHECK-NEXT: .LBB0_3: # %do_cmpxchg
-; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
-; CHECK-NEXT: # => This Inner Loop Header: Depth=2
-; CHECK-NEXT: lr.w.aqrl a3, (a0)
-; CHECK-NEXT: bne a3, a1, .LBB0_1
-; CHECK-NEXT: # %bb.4: # %do_cmpxchg
-; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=2
-; CHECK-NEXT: sc.w.rl a4, a2, (a0)
-; CHECK-NEXT: bnez a4, .LBB0_3
-; CHECK-NEXT: # %bb.5: # %do_cmpxchg
-; CHECK-NEXT: # %bb.2: # %exit
-; CHECK-NEXT: ret
+; NOZACAS-LABEL: cmpxchg_and_branch1:
+; NOZACAS: # %bb.0: # %entry
+; NOZACAS-NEXT: .LBB0_1: # %do_cmpxchg
+; NOZACAS-NEXT: # =>This Loop Header: Depth=1
+; NOZACAS-NEXT: # Child Loop BB0_3 Depth 2
+; NOZACAS-NEXT: .LBB0_3: # %do_cmpxchg
+; NOZACAS-NEXT: # Parent Loop BB0_1 Depth=1
+; NOZACAS-NEXT: # => This Inner Loop Header: Depth=2
+; NOZACAS-NEXT: lr.w.aqrl a3, (a0)
+; NOZACAS-NEXT: bne a3, a1, .LBB0_1
+; NOZACAS-NEXT: # %bb.4: # %do_cmpxchg
+; NOZACAS-NEXT: # in Loop: Header=BB0_3 Depth=2
+; NOZACAS-NEXT: sc.w.rl a4, a2, (a0)
+; NOZACAS-NEXT: bnez a4, .LBB0_3
+; NOZACAS-NEXT: # %bb.5: # %do_cmpxchg
+; NOZACAS-NEXT: # %bb.2: # %exit
+; NOZACAS-NEXT: ret
+;
+; ZACAS-LABEL: cmpxchg_and_branch1:
+; ZACAS: # %bb.0: # %entry
+; ZACAS-NEXT: .LBB0_1: # %do_cmpxchg
+; ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; ZACAS-NEXT: mv a3, a1
+; ZACAS-NEXT: amocas.w.aqrl a3, a2, (a0)
+; ZACAS-NEXT: bne a3, a1, .LBB0_1
+; ZACAS-NEXT: # %bb.2: # %exit
+; ZACAS-NEXT: ret
entry:
br label %do_cmpxchg
do_cmpxchg:
@@ -36,25 +50,35 @@ exit:
}
define void @cmpxchg_and_branch2(ptr %ptr, i32 signext %cmp, i32 signext %val) nounwind {
-; CHECK-LABEL: cmpxchg_and_branch2:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: .LBB1_1: # %do_cmpxchg
-; CHECK-NEXT: # =>This Loop Header: Depth=1
-; CHECK-NEXT: # Child Loop BB1_3 Depth 2
-; CHECK-NEXT: .LBB1_3: # %do_cmpxchg
-; CHECK-NEXT: # Parent Loop BB1_1 Depth=1
-; CHECK-NEXT: # => This Inner Loop Header: Depth=2
-; CHECK-NEXT: lr.w.aqrl a3, (a0)
-; CHECK-NEXT: bne a3, a1, .LBB1_5
-; CHECK-NEXT: # %bb.4: # %do_cmpxchg
-; CHECK-NEXT: # in Loop: Header=BB1_3 Depth=2
-; CHECK-NEXT: sc.w.rl a4, a2, (a0)
-; CHECK-NEXT: bnez a4, .LBB1_3
-; CHECK-NEXT: .LBB1_5: # %do_cmpxchg
-; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1
-; CHECK-NEXT: beq a3, a1, .LBB1_1
-; CHECK-NEXT: # %bb.2: # %exit
-; CHECK-NEXT: ret
+; NOZACAS-LABEL: cmpxchg_and_branch2:
+; NOZACAS: # %bb.0: # %entry
+; NOZACAS-NEXT: .LBB1_1: # %do_cmpxchg
+; NOZACAS-NEXT: # =>This Loop Header: Depth=1
+; NOZACAS-NEXT: # Child Loop BB1_3 Depth 2
+; NOZACAS-NEXT: .LBB1_3: # %do_cmpxchg
+; NOZACAS-NEXT: # Parent Loop BB1_1 Depth=1
+; NOZACAS-NEXT: # => This Inner Loop Header: Depth=2
+; NOZACAS-NEXT: lr.w.aqrl a3, (a0)
+; NOZACAS-NEXT: bne a3, a1, .LBB1_5
+; NOZACAS-NEXT: # %bb.4: # %do_cmpxchg
+; NOZACAS-NEXT: # in Loop: Header=BB1_3 Depth=2
+; NOZACAS-NEXT: sc.w.rl a4, a2, (a0)
+; NOZACAS-NEXT: bnez a4, .LBB1_3
+; NOZACAS-NEXT: .LBB1_5: # %do_cmpxchg
+; NOZACAS-NEXT: # in Loop: Header=BB1_1 Depth=1
+; NOZACAS-NEXT: beq a3, a1, .LBB1_1
+; NOZACAS-NEXT: # %bb.2: # %exit
+; NOZACAS-NEXT: ret
+;
+; ZACAS-LABEL: cmpxchg_and_branch2:
+; ZACAS: # %bb.0: # %entry
+; ZACAS-NEXT: .LBB1_1: # %do_cmpxchg
+; ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; ZACAS-NEXT: mv a3, a1
+; ZACAS-NEXT: amocas.w.aqrl a3, a2, (a0)
+; ZACAS-NEXT: beq a3, a1, .LBB1_1
+; ZACAS-NEXT: # %bb.2: # %exit
+; ZACAS-NEXT: ret
entry:
br label %do_cmpxchg
do_cmpxchg:
@@ -96,6 +120,36 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v
; RV32IA-NEXT: # %bb.2: # %exit
; RV32IA-NEXT: ret
;
+; RV32IA-ZACAS-LABEL: cmpxchg_masked_and_branch1:
+; RV32IA-ZACAS: # %bb.0: # %entry
+; RV32IA-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-ZACAS-NEXT: slli a4, a0, 3
+; RV32IA-ZACAS-NEXT: li a0, 255
+; RV32IA-ZACAS-NEXT: sll a0, a0, a4
+; RV32IA-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-ZACAS-NEXT: sll a1, a1, a4
+; RV32IA-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-ZACAS-NEXT: sll a2, a2, a4
+; RV32IA-ZACAS-NEXT: .LBB2_1: # %do_cmpxchg
+; RV32IA-ZACAS-NEXT: # =>This Loop Header: Depth=1
+; RV32IA-ZACAS-NEXT: # Child Loop BB2_3 Depth 2
+; RV32IA-ZACAS-NEXT: .LBB2_3: # %do_cmpxchg
+; RV32IA-ZACAS-NEXT: # Parent Loop BB2_1 Depth=1
+; RV32IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2
+; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a3)
+; RV32IA-ZACAS-NEXT: and a5, a4, a0
+; RV32IA-ZACAS-NEXT: bne a5, a1, .LBB2_1
+; RV32IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg
+; RV32IA-ZACAS-NEXT: # in Loop: Header=BB2_3 Depth=2
+; RV32IA-ZACAS-NEXT: xor a5, a4, a2
+; RV32IA-ZACAS-NEXT: and a5, a5, a0
+; RV32IA-ZACAS-NEXT: xor a5, a4, a5
+; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV32IA-ZACAS-NEXT: bnez a5, .LBB2_3
+; RV32IA-ZACAS-NEXT: # %bb.5: # %do_cmpxchg
+; RV32IA-ZACAS-NEXT: # %bb.2: # %exit
+; RV32IA-ZACAS-NEXT: ret
+;
; RV64IA-LABEL: cmpxchg_masked_and_branch1:
; RV64IA: # %bb.0: # %entry
; RV64IA-NEXT: andi a3, a0, -4
@@ -125,6 +179,36 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v
; RV64IA-NEXT: # %bb.5: # %do_cmpxchg
; RV64IA-NEXT: # %bb.2: # %exit
; RV64IA-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_masked_and_branch1:
+; RV64IA-ZACAS: # %bb.0: # %entry
+; RV64IA-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-ZACAS-NEXT: slli a4, a0, 3
+; RV64IA-ZACAS-NEXT: li a0, 255
+; RV64IA-ZACAS-NEXT: sllw a0, a0, a4
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a4
+; RV64IA-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-ZACAS-NEXT: sllw a2, a2, a4
+; RV64IA-ZACAS-NEXT: .LBB2_1: # %do_cmpxchg
+; RV64IA-ZACAS-NEXT: # =>This Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: # Child Loop BB2_3 Depth 2
+; RV64IA-ZACAS-NEXT: .LBB2_3: # %do_cmpxchg
+; RV64IA-ZACAS-NEXT: # Parent Loop BB2_1 Depth=1
+; RV64IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a3)
+; RV64IA-ZACAS-NEXT: and a5, a4, a0
+; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB2_1
+; RV64IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg
+; RV64IA-ZACAS-NEXT: # in Loop: Header=BB2_3 Depth=2
+; RV64IA-ZACAS-NEXT: xor a5, a4, a2
+; RV64IA-ZACAS-NEXT: and a5, a5, a0
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB2_3
+; RV64IA-ZACAS-NEXT: # %bb.5: # %do_cmpxchg
+; RV64IA-ZACAS-NEXT: # %bb.2: # %exit
+; RV64IA-ZACAS-NEXT: ret
entry:
br label %do_cmpxchg
do_cmpxchg:
@@ -169,6 +253,39 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v
; RV32IA-NEXT: # %bb.2: # %exit
; RV32IA-NEXT: ret
;
+; RV32IA-ZACAS-LABEL: cmpxchg_masked_and_branch2:
+; RV32IA-ZACAS: # %bb.0: # %entry
+; RV32IA-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-ZACAS-NEXT: slli a4, a0, 3
+; RV32IA-ZACAS-NEXT: li a0, 255
+; RV32IA-ZACAS-NEXT: sll a0, a0, a4
+; RV32IA-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-ZACAS-NEXT: sll a1, a1, a4
+; RV32IA-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-ZACAS-NEXT: sll a2, a2, a4
+; RV32IA-ZACAS-NEXT: .LBB3_1: # %do_cmpxchg
+; RV32IA-ZACAS-NEXT: # =>This Loop Header: Depth=1
+; RV32IA-ZACAS-NEXT: # Child Loop BB3_3 Depth 2
+; RV32IA-ZACAS-NEXT: .LBB3_3: # %do_cmpxchg
+; RV32IA-ZACAS-NEXT: # Parent Loop BB3_1 Depth=1
+; RV32IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2
+; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a3)
+; RV32IA-ZACAS-NEXT: and a5, a4, a0
+; RV32IA-ZACAS-NEXT: bne a5, a1, .LBB3_5
+; RV32IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg
+; RV32IA-ZACAS-NEXT: # in Loop: Header=BB3_3 Depth=2
+; RV32IA-ZACAS-NEXT: xor a5, a4, a2
+; RV32IA-ZACAS-NEXT: and a5, a5, a0
+; RV32IA-ZACAS-NEXT: xor a5, a4, a5
+; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV32IA-ZACAS-NEXT: bnez a5, .LBB3_3
+; RV32IA-ZACAS-NEXT: .LBB3_5: # %do_cmpxchg
+; RV32IA-ZACAS-NEXT: # in Loop: Header=BB3_1 Depth=1
+; RV32IA-ZACAS-NEXT: and a4, a4, a0
+; RV32IA-ZACAS-NEXT: beq a1, a4, .LBB3_1
+; RV32IA-ZACAS-NEXT: # %bb.2: # %exit
+; RV32IA-ZACAS-NEXT: ret
+;
; RV64IA-LABEL: cmpxchg_masked_and_branch2:
; RV64IA: # %bb.0: # %entry
; RV64IA-NEXT: andi a3, a0, -4
@@ -201,6 +318,39 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v
; RV64IA-NEXT: beq a1, a4, .LBB3_1
; RV64IA-NEXT: # %bb.2: # %exit
; RV64IA-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_masked_and_branch2:
+; RV64IA-ZACAS: # %bb.0: # %entry
+; RV64IA-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-ZACAS-NEXT: slli a4, a0, 3
+; RV64IA-ZACAS-NEXT: li a0, 255
+; RV64IA-ZACAS-NEXT: sllw a0, a0, a4
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a4
+; RV64IA-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-ZACAS-NEXT: sllw a2, a2, a4
+; RV64IA-ZACAS-NEXT: .LBB3_1: # %do_cmpxchg
+; RV64IA-ZACAS-NEXT: # =>This Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: # Child Loop BB3_3 Depth 2
+; RV64IA-ZACAS-NEXT: .LBB3_3: # %do_cmpxchg
+; RV64IA-ZACAS-NEXT: # Parent Loop BB3_1 Depth=1
+; RV64IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a3)
+; RV64IA-ZACAS-NEXT: and a5, a4, a0
+; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB3_5
+; RV64IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg
+; RV64IA-ZACAS-NEXT: # in Loop: Header=BB3_3 Depth=2
+; RV64IA-ZACAS-NEXT: xor a5, a4, a2
+; RV64IA-ZACAS-NEXT: and a5, a5, a0
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB3_3
+; RV64IA-ZACAS-NEXT: .LBB3_5: # %do_cmpxchg
+; RV64IA-ZACAS-NEXT: # in Loop: Header=BB3_1 Depth=1
+; RV64IA-ZACAS-NEXT: and a4, a4, a0
+; RV64IA-ZACAS-NEXT: beq a1, a4, .LBB3_1
+; RV64IA-ZACAS-NEXT: # %bb.2: # %exit
+; RV64IA-ZACAS-NEXT: ret
entry:
br label %do_cmpxchg
do_cmpxchg:
@@ -212,25 +362,35 @@ exit:
}
define void @cmpxchg_and_irrelevant_branch(ptr %ptr, i32 signext %cmp, i32 signext %val, i1 zeroext %bool) nounwind {
-; CHECK-LABEL: cmpxchg_and_irrelevant_branch:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: .LBB4_1: # %do_cmpxchg
-; CHECK-NEXT: # =>This Loop Header: Depth=1
-; CHECK-NEXT: # Child Loop BB4_3 Depth 2
-; CHECK-NEXT: .LBB4_3: # %do_cmpxchg
-; CHECK-NEXT: # Parent Loop BB4_1 Depth=1
-; CHECK-NEXT: # => This Inner Loop Header: Depth=2
-; CHECK-NEXT: lr.w.aqrl a4, (a0)
-; CHECK-NEXT: bne a4, a1, .LBB4_5
-; CHECK-NEXT: # %bb.4: # %do_cmpxchg
-; CHECK-NEXT: # in Loop: Header=BB4_3 Depth=2
-; CHECK-NEXT: sc.w.rl a5, a2, (a0)
-; CHECK-NEXT: bnez a5, .LBB4_3
-; CHECK-NEXT: .LBB4_5: # %do_cmpxchg
-; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1
-; CHECK-NEXT: beqz a3, .LBB4_1
-; CHECK-NEXT: # %bb.2: # %exit
-; CHECK-NEXT: ret
+; NOZACAS-LABEL: cmpxchg_and_irrelevant_branch:
+; NOZACAS: # %bb.0: # %entry
+; NOZACAS-NEXT: .LBB4_1: # %do_cmpxchg
+; NOZACAS-NEXT: # =>This Loop Header: Depth=1
+; NOZACAS-NEXT: # Child Loop BB4_3 Depth 2
+; NOZACAS-NEXT: .LBB4_3: # %do_cmpxchg
+; NOZACAS-NEXT: # Parent Loop BB4_1 Depth=1
+; NOZACAS-NEXT: # => This Inner Loop Header: Depth=2
+; NOZACAS-NEXT: lr.w.aqrl a4, (a0)
+; NOZACAS-NEXT: bne a4, a1, .LBB4_5
+; NOZACAS-NEXT: # %bb.4: # %do_cmpxchg
+; NOZACAS-NEXT: # in Loop: Header=BB4_3 Depth=2
+; NOZACAS-NEXT: sc.w.rl a5, a2, (a0)
+; NOZACAS-NEXT: bnez a5, .LBB4_3
+; NOZACAS-NEXT: .LBB4_5: # %do_cmpxchg
+; NOZACAS-NEXT: # in Loop: Header=BB4_1 Depth=1
+; NOZACAS-NEXT: beqz a3, .LBB4_1
+; NOZACAS-NEXT: # %bb.2: # %exit
+; NOZACAS-NEXT: ret
+;
+; ZACAS-LABEL: cmpxchg_and_irrelevant_branch:
+; ZACAS: # %bb.0: # %entry
+; ZACAS-NEXT: .LBB4_1: # %do_cmpxchg
+; ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; ZACAS-NEXT: mv a4, a1
+; ZACAS-NEXT: amocas.w.aqrl a4, a2, (a0)
+; ZACAS-NEXT: beqz a3, .LBB4_1
+; ZACAS-NEXT: # %bb.2: # %exit
+; ZACAS-NEXT: ret
entry:
br label %do_cmpxchg
do_cmpxchg:
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
index 46ed01b11584f9..b3c9224646ed98 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
@@ -3,14 +3,22 @@
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s
+; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZACAS,RV32IA-WMO-ZACAS %s
; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s
+; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+experimental-zacas -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZACAS,RV32IA-TSO-ZACAS %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-WMO-ZACAS %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zacas -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-TSO-ZACAS %s
define void @cmpxchg_i8_monotonic_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic:
@@ -125,6 +133,29 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-WMO-NEXT: .LBB1_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_acquire_monotonic:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: li a4, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB1_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB1_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB1_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i8_acquire_monotonic:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -148,6 +179,29 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-TSO-NEXT: .LBB1_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_acquire_monotonic:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: li a4, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB1_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB1_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB1_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i8_acquire_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -184,6 +238,29 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-NEXT: .LBB1_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_acquire_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB1_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB1_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB1_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -206,6 +283,29 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-NEXT: bnez a5, .LBB1_1
; RV64IA-TSO-NEXT: .LBB1_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_acquire_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB1_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB1_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB1_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire monotonic
ret void
}
@@ -247,6 +347,29 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-WMO-NEXT: .LBB2_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_acquire_acquire:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: li a4, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB2_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB2_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB2_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i8_acquire_acquire:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -270,6 +393,29 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-TSO-NEXT: .LBB2_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_acquire_acquire:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: li a4, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB2_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB2_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB2_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i8_acquire_acquire:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -306,6 +452,29 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-NEXT: .LBB2_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_acquire_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB2_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB2_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB2_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -328,6 +497,29 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-NEXT: bnez a5, .LBB2_1
; RV64IA-TSO-NEXT: .LBB2_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_acquire_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB2_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB2_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB2_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire acquire
ret void
}
@@ -369,6 +561,29 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-WMO-NEXT: .LBB3_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_release_monotonic:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: li a4, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB3_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB3_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB3_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i8_release_monotonic:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -392,6 +607,29 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-TSO-NEXT: .LBB3_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_release_monotonic:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: li a4, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB3_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB3_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB3_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i8_release_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -428,6 +666,29 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-NEXT: .LBB3_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_release_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB3_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB3_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB3_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -450,6 +711,29 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-NEXT: bnez a5, .LBB3_1
; RV64IA-TSO-NEXT: .LBB3_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_release_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB3_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB3_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB3_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release monotonic
ret void
}
@@ -491,6 +775,29 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-WMO-NEXT: .LBB4_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_release_acquire:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: li a4, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB4_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB4_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB4_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i8_release_acquire:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -514,6 +821,29 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-TSO-NEXT: .LBB4_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_release_acquire:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: li a4, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB4_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB4_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB4_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i8_release_acquire:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -550,6 +880,29 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-NEXT: .LBB4_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_release_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB4_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB4_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB4_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -572,6 +925,29 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-NEXT: bnez a5, .LBB4_1
; RV64IA-TSO-NEXT: .LBB4_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_release_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB4_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB4_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB4_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release acquire
ret void
}
@@ -613,6 +989,29 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-WMO-NEXT: .LBB5_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_acq_rel_monotonic:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: li a4, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB5_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB5_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB5_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -636,6 +1035,29 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-TSO-NEXT: .LBB5_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_acq_rel_monotonic:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: li a4, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB5_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB5_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB5_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -672,6 +1094,29 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-NEXT: .LBB5_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_acq_rel_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB5_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB5_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB5_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -694,6 +1139,29 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-NEXT: bnez a5, .LBB5_1
; RV64IA-TSO-NEXT: .LBB5_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_acq_rel_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB5_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB5_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB5_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel monotonic
ret void
}
@@ -735,6 +1203,29 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-WMO-NEXT: .LBB6_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i8_acq_rel_acquire:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: li a4, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB6_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB6_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB6_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -758,6 +1249,29 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-TSO-NEXT: .LBB6_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i8_acq_rel_acquire:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: li a4, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a4, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB6_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV32IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB6_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB6_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -794,6 +1308,29 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-NEXT: .LBB6_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i8_acq_rel_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: bne a5, a1, .LBB6_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB6_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB6_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -816,6 +1353,29 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-NEXT: bnez a5, .LBB6_1
; RV64IA-TSO-NEXT: .LBB6_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i8_acq_rel_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: bne a5, a1, .LBB6_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB6_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB6_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel acquire
ret void
}
@@ -1164,6 +1724,30 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV32IA-WMO-NEXT: .LBB11_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_acquire_monotonic:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB11_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB11_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB11_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i16_acquire_monotonic:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -1188,6 +1772,30 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV32IA-TSO-NEXT: .LBB11_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_acquire_monotonic:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB11_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB11_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB11_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i16_acquire_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1225,6 +1833,30 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-NEXT: .LBB11_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_acquire_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB11_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB11_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB11_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1248,6 +1880,30 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-NEXT: bnez a4, .LBB11_1
; RV64IA-TSO-NEXT: .LBB11_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_acquire_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB11_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB11_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB11_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire monotonic
ret void
}
@@ -1290,6 +1946,30 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV32IA-WMO-NEXT: .LBB12_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_acquire_acquire:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB12_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB12_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB12_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i16_acquire_acquire:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -1314,6 +1994,30 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV32IA-TSO-NEXT: .LBB12_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_acquire_acquire:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB12_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB12_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB12_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i16_acquire_acquire:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1351,6 +2055,30 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-NEXT: .LBB12_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_acquire_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB12_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB12_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB12_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1374,6 +2102,30 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-NEXT: bnez a4, .LBB12_1
; RV64IA-TSO-NEXT: .LBB12_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_acquire_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB12_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB12_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB12_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire acquire
ret void
}
@@ -1416,6 +2168,30 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV32IA-WMO-NEXT: .LBB13_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_release_monotonic:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB13_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB13_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB13_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i16_release_monotonic:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -1440,6 +2216,30 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV32IA-TSO-NEXT: .LBB13_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_release_monotonic:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB13_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB13_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB13_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i16_release_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1477,6 +2277,30 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-NEXT: .LBB13_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_release_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB13_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB13_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB13_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1500,6 +2324,30 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-NEXT: bnez a4, .LBB13_1
; RV64IA-TSO-NEXT: .LBB13_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_release_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB13_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB13_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB13_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release monotonic
ret void
}
@@ -1542,6 +2390,30 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV32IA-WMO-NEXT: .LBB14_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_release_acquire:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB14_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB14_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB14_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i16_release_acquire:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -1566,6 +2438,30 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV32IA-TSO-NEXT: .LBB14_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_release_acquire:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB14_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB14_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB14_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i16_release_acquire:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1603,6 +2499,30 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-NEXT: .LBB14_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_release_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB14_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB14_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB14_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1626,6 +2546,30 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-NEXT: bnez a4, .LBB14_1
; RV64IA-TSO-NEXT: .LBB14_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_release_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB14_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB14_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB14_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release acquire
ret void
}
@@ -1668,6 +2612,30 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV32IA-WMO-NEXT: .LBB15_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_acq_rel_monotonic:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB15_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB15_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB15_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -1692,6 +2660,30 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV32IA-TSO-NEXT: .LBB15_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_acq_rel_monotonic:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB15_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB15_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB15_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1729,6 +2721,30 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-NEXT: .LBB15_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_acq_rel_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB15_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB15_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB15_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1752,6 +2768,30 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-NEXT: bnez a4, .LBB15_1
; RV64IA-TSO-NEXT: .LBB15_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_acq_rel_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB15_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB15_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB15_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel monotonic
ret void
}
@@ -1794,6 +2834,30 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV32IA-WMO-NEXT: .LBB16_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i16_acq_rel_acquire:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV32IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-WMO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV32IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB16_3
+; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
+; RV32IA-WMO-ZACAS-NEXT: bnez a4, .LBB16_1
+; RV32IA-WMO-ZACAS-NEXT: .LBB16_3:
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: andi a3, a0, -4
@@ -1818,6 +2882,30 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV32IA-TSO-NEXT: .LBB16_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i16_acq_rel_acquire:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV32IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV32IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV32IA-TSO-ZACAS-NEXT: sll a5, a4, a0
+; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0
+; RV32IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sll a0, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV32IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV32IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB16_3
+; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV32IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV32IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV32IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV32IA-TSO-ZACAS-NEXT: bnez a4, .LBB16_1
+; RV32IA-TSO-ZACAS-NEXT: .LBB16_3:
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -1855,6 +2943,30 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-NEXT: .LBB16_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i16_acq_rel_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a2, (a3)
+; RV64IA-WMO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-WMO-ZACAS-NEXT: bne a4, a1, .LBB16_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-WMO-ZACAS-NEXT: bnez a4, .LBB16_1
+; RV64IA-WMO-ZACAS-NEXT: .LBB16_3:
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1878,6 +2990,30 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-NEXT: bnez a4, .LBB16_1
; RV64IA-TSO-NEXT: .LBB16_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i16_acq_rel_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-TSO-ZACAS-NEXT: bne a4, a1, .LBB16_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-TSO-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB16_1
+; RV64IA-TSO-ZACAS-NEXT: .LBB16_3:
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel acquire
ret void
}
@@ -2130,16 +3266,32 @@ define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounw
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: cmpxchg_i32_monotonic_monotonic:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT: lr.w a3, (a0)
-; RV32IA-NEXT: bne a3, a1, .LBB20_3
-; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
-; RV32IA-NEXT: sc.w a4, a2, (a0)
-; RV32IA-NEXT: bnez a4, .LBB20_1
-; RV32IA-NEXT: .LBB20_3:
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: cmpxchg_i32_monotonic_monotonic:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-NEXT: lr.w a3, (a0)
+; RV32IA-WMO-NEXT: bne a3, a1, .LBB20_3
+; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
+; RV32IA-WMO-NEXT: sc.w a4, a2, (a0)
+; RV32IA-WMO-NEXT: bnez a4, .LBB20_1
+; RV32IA-WMO-NEXT: .LBB20_3:
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-ZACAS-LABEL: cmpxchg_i32_monotonic_monotonic:
+; RV32IA-ZACAS: # %bb.0:
+; RV32IA-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV32IA-ZACAS-NEXT: ret
+;
+; RV32IA-TSO-LABEL: cmpxchg_i32_monotonic_monotonic:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-NEXT: lr.w a3, (a0)
+; RV32IA-TSO-NEXT: bne a3, a1, .LBB20_3
+; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
+; RV32IA-TSO-NEXT: sc.w a4, a2, (a0)
+; RV32IA-TSO-NEXT: bnez a4, .LBB20_1
+; RV32IA-TSO-NEXT: .LBB20_3:
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV64I: # %bb.0:
@@ -2154,17 +3306,35 @@ define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounw
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: sext.w a1, a1
-; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a3, (a0)
-; RV64IA-NEXT: bne a3, a1, .LBB20_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
-; RV64IA-NEXT: sc.w a4, a2, (a0)
-; RV64IA-NEXT: bnez a4, .LBB20_1
-; RV64IA-NEXT: .LBB20_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i32_monotonic_monotonic:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: sext.w a1, a1
+; RV64IA-WMO-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a3, (a0)
+; RV64IA-WMO-NEXT: bne a3, a1, .LBB20_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w a4, a2, (a0)
+; RV64IA-WMO-NEXT: bnez a4, .LBB20_1
+; RV64IA-WMO-NEXT: .LBB20_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_i32_monotonic_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i32_monotonic_monotonic:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: sext.w a1, a1
+; RV64IA-TSO-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a0)
+; RV64IA-TSO-NEXT: bne a3, a1, .LBB20_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a4, a2, (a0)
+; RV64IA-TSO-NEXT: bnez a4, .LBB20_1
+; RV64IA-TSO-NEXT: .LBB20_3:
+; RV64IA-TSO-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val monotonic monotonic
ret void
}
@@ -2194,6 +3364,11 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV32IA-WMO-NEXT: .LBB21_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_acquire_monotonic:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0)
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i32_acquire_monotonic:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
@@ -2205,6 +3380,11 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV32IA-TSO-NEXT: .LBB21_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_acquire_monotonic:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i32_acquire_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2230,6 +3410,12 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-WMO-NEXT: .LBB21_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acquire_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -2241,6 +3427,12 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-TSO-NEXT: bnez a4, .LBB21_1
; RV64IA-TSO-NEXT: .LBB21_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acquire_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire monotonic
ret void
}
@@ -2270,6 +3462,11 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV32IA-WMO-NEXT: .LBB22_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_acquire_acquire:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0)
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i32_acquire_acquire:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
@@ -2281,6 +3478,11 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV32IA-TSO-NEXT: .LBB22_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_acquire_acquire:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i32_acquire_acquire:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2306,6 +3508,12 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-NEXT: .LBB22_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acquire_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -2317,6 +3525,12 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-NEXT: bnez a4, .LBB22_1
; RV64IA-TSO-NEXT: .LBB22_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acquire_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire acquire
ret void
}
@@ -2346,6 +3560,11 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV32IA-WMO-NEXT: .LBB23_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_release_monotonic:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: amocas.w.rl a1, a2, (a0)
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i32_release_monotonic:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
@@ -2357,6 +3576,11 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV32IA-TSO-NEXT: .LBB23_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_release_monotonic:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i32_release_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2382,6 +3606,12 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-WMO-NEXT: .LBB23_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_release_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-WMO-ZACAS-NEXT: amocas.w.rl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -2393,6 +3623,12 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-TSO-NEXT: bnez a4, .LBB23_1
; RV64IA-TSO-NEXT: .LBB23_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_release_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release monotonic
ret void
}
@@ -2422,6 +3658,11 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV32IA-WMO-NEXT: .LBB24_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_release_acquire:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i32_release_acquire:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
@@ -2433,6 +3674,11 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV32IA-TSO-NEXT: .LBB24_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_release_acquire:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i32_release_acquire:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2458,6 +3704,12 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-NEXT: .LBB24_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_release_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -2469,6 +3721,12 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-NEXT: bnez a4, .LBB24_1
; RV64IA-TSO-NEXT: .LBB24_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_release_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release acquire
ret void
}
@@ -2498,6 +3756,11 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV32IA-WMO-NEXT: .LBB25_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_acq_rel_monotonic:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
@@ -2509,6 +3772,11 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV32IA-TSO-NEXT: .LBB25_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_acq_rel_monotonic:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2534,6 +3802,12 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-WMO-NEXT: .LBB25_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acq_rel_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -2545,6 +3819,12 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-TSO-NEXT: bnez a4, .LBB25_1
; RV64IA-TSO-NEXT: .LBB25_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acq_rel_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel monotonic
ret void
}
@@ -2574,6 +3854,11 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV32IA-WMO-NEXT: .LBB26_3:
; RV32IA-WMO-NEXT: ret
;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_acq_rel_acquire:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
; RV32IA-TSO-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
@@ -2585,6 +3870,11 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV32IA-TSO-NEXT: .LBB26_3:
; RV32IA-TSO-NEXT: ret
;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_acq_rel_acquire:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV32IA-TSO-ZACAS-NEXT: ret
+;
; RV64I-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -2610,6 +3900,12 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-NEXT: .LBB26_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_acq_rel_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -2621,6 +3917,12 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-NEXT: bnez a4, .LBB26_1
; RV64IA-TSO-NEXT: .LBB26_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_acq_rel_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel acquire
ret void
}
@@ -2639,16 +3941,37 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT: lr.w.aqrl a3, (a0)
-; RV32IA-NEXT: bne a3, a1, .LBB27_3
-; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
-; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
-; RV32IA-NEXT: bnez a4, .LBB27_1
-; RV32IA-NEXT: .LBB27_3:
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: cmpxchg_i32_seq_cst_monotonic:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-NEXT: lr.w.aqrl a3, (a0)
+; RV32IA-WMO-NEXT: bne a3, a1, .LBB27_3
+; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
+; RV32IA-WMO-NEXT: sc.w.rl a4, a2, (a0)
+; RV32IA-WMO-NEXT: bnez a4, .LBB27_1
+; RV32IA-WMO-NEXT: .LBB27_3:
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_monotonic:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
+; RV32IA-TSO-LABEL: cmpxchg_i32_seq_cst_monotonic:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-NEXT: lr.w.aqrl a3, (a0)
+; RV32IA-TSO-NEXT: bne a3, a1, .LBB27_3
+; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
+; RV32IA-TSO-NEXT: sc.w.rl a4, a2, (a0)
+; RV32IA-TSO-NEXT: bnez a4, .LBB27_1
+; RV32IA-TSO-NEXT: .LBB27_3:
+; RV32IA-TSO-NEXT: ret
+;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_monotonic:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV32IA-TSO-ZACAS-NEXT: ret
;
; RV64I-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV64I: # %bb.0:
@@ -2663,17 +3986,41 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: sext.w a1, a1
-; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a3, (a0)
-; RV64IA-NEXT: bne a3, a1, .LBB27_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
-; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
-; RV64IA-NEXT: bnez a4, .LBB27_1
-; RV64IA-NEXT: .LBB27_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i32_seq_cst_monotonic:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: sext.w a1, a1
+; RV64IA-WMO-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-WMO-NEXT: bne a3, a1, .LBB27_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a4, a2, (a0)
+; RV64IA-WMO-NEXT: bnez a4, .LBB27_1
+; RV64IA-WMO-NEXT: .LBB27_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_monotonic:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: sext.w a1, a1
+; RV64IA-TSO-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-TSO-NEXT: bne a3, a1, .LBB27_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w.rl a4, a2, (a0)
+; RV64IA-TSO-NEXT: bnez a4, .LBB27_1
+; RV64IA-TSO-NEXT: .LBB27_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst monotonic
ret void
}
@@ -2692,16 +4039,37 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: cmpxchg_i32_seq_cst_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT: lr.w.aqrl a3, (a0)
-; RV32IA-NEXT: bne a3, a1, .LBB28_3
-; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
-; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
-; RV32IA-NEXT: bnez a4, .LBB28_1
-; RV32IA-NEXT: .LBB28_3:
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: cmpxchg_i32_seq_cst_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-NEXT: lr.w.aqrl a3, (a0)
+; RV32IA-WMO-NEXT: bne a3, a1, .LBB28_3
+; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
+; RV32IA-WMO-NEXT: sc.w.rl a4, a2, (a0)
+; RV32IA-WMO-NEXT: bnez a4, .LBB28_1
+; RV32IA-WMO-NEXT: .LBB28_3:
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_acquire:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
+; RV32IA-TSO-LABEL: cmpxchg_i32_seq_cst_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-NEXT: lr.w.aqrl a3, (a0)
+; RV32IA-TSO-NEXT: bne a3, a1, .LBB28_3
+; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
+; RV32IA-TSO-NEXT: sc.w.rl a4, a2, (a0)
+; RV32IA-TSO-NEXT: bnez a4, .LBB28_1
+; RV32IA-TSO-NEXT: .LBB28_3:
+; RV32IA-TSO-NEXT: ret
+;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_acquire:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV32IA-TSO-ZACAS-NEXT: ret
;
; RV64I-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV64I: # %bb.0:
@@ -2716,17 +4084,41 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: sext.w a1, a1
-; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a3, (a0)
-; RV64IA-NEXT: bne a3, a1, .LBB28_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
-; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
-; RV64IA-NEXT: bnez a4, .LBB28_1
-; RV64IA-NEXT: .LBB28_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i32_seq_cst_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: sext.w a1, a1
+; RV64IA-WMO-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-WMO-NEXT: bne a3, a1, .LBB28_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a4, a2, (a0)
+; RV64IA-WMO-NEXT: bnez a4, .LBB28_1
+; RV64IA-WMO-NEXT: .LBB28_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: sext.w a1, a1
+; RV64IA-TSO-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-TSO-NEXT: bne a3, a1, .LBB28_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w.rl a4, a2, (a0)
+; RV64IA-TSO-NEXT: bnez a4, .LBB28_1
+; RV64IA-TSO-NEXT: .LBB28_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst acquire
ret void
}
@@ -2745,16 +4137,37 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT: lr.w.aqrl a3, (a0)
-; RV32IA-NEXT: bne a3, a1, .LBB29_3
-; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
-; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
-; RV32IA-NEXT: bnez a4, .LBB29_1
-; RV32IA-NEXT: .LBB29_3:
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-WMO-NEXT: lr.w.aqrl a3, (a0)
+; RV32IA-WMO-NEXT: bne a3, a1, .LBB29_3
+; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
+; RV32IA-WMO-NEXT: sc.w.rl a4, a2, (a0)
+; RV32IA-WMO-NEXT: bnez a4, .LBB29_1
+; RV32IA-WMO-NEXT: .LBB29_3:
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV32IA-WMO-ZACAS: # %bb.0:
+; RV32IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV32IA-WMO-ZACAS-NEXT: ret
+;
+; RV32IA-TSO-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
+; RV32IA-TSO-NEXT: lr.w.aqrl a3, (a0)
+; RV32IA-TSO-NEXT: bne a3, a1, .LBB29_3
+; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
+; RV32IA-TSO-NEXT: sc.w.rl a4, a2, (a0)
+; RV32IA-TSO-NEXT: bnez a4, .LBB29_1
+; RV32IA-TSO-NEXT: .LBB29_3:
+; RV32IA-TSO-NEXT: ret
+;
+; RV32IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV32IA-TSO-ZACAS: # %bb.0:
+; RV32IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV32IA-TSO-ZACAS-NEXT: ret
;
; RV64I-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64I: # %bb.0:
@@ -2769,17 +4182,41 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: sext.w a1, a1
-; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a3, (a0)
-; RV64IA-NEXT: bne a3, a1, .LBB29_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
-; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
-; RV64IA-NEXT: bnez a4, .LBB29_1
-; RV64IA-NEXT: .LBB29_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: sext.w a1, a1
+; RV64IA-WMO-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-WMO-NEXT: bne a3, a1, .LBB29_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a4, a2, (a0)
+; RV64IA-WMO-NEXT: bnez a4, .LBB29_1
+; RV64IA-WMO-NEXT: .LBB29_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: sext.w a1, a1
+; RV64IA-TSO-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-TSO-NEXT: bne a3, a1, .LBB29_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w.rl a4, a2, (a0)
+; RV64IA-TSO-NEXT: bnez a4, .LBB29_1
+; RV64IA-TSO-NEXT: .LBB29_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: sext.w a1, a1
+; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst
ret void
}
@@ -2830,16 +4267,32 @@ define void @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounw
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i64_monotonic_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.d a3, (a0)
-; RV64IA-NEXT: bne a3, a1, .LBB30_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1
-; RV64IA-NEXT: sc.d a4, a2, (a0)
-; RV64IA-NEXT: bnez a4, .LBB30_1
-; RV64IA-NEXT: .LBB30_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i64_monotonic_monotonic:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.d a3, (a0)
+; RV64IA-WMO-NEXT: bne a3, a1, .LBB30_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1
+; RV64IA-WMO-NEXT: sc.d a4, a2, (a0)
+; RV64IA-WMO-NEXT: bnez a4, .LBB30_1
+; RV64IA-WMO-NEXT: .LBB30_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_i64_monotonic_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i64_monotonic_monotonic:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.d a3, (a0)
+; RV64IA-TSO-NEXT: bne a3, a1, .LBB30_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1
+; RV64IA-TSO-NEXT: sc.d a4, a2, (a0)
+; RV64IA-TSO-NEXT: bnez a4, .LBB30_1
+; RV64IA-TSO-NEXT: .LBB30_3:
+; RV64IA-TSO-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val monotonic monotonic
ret void
}
@@ -2903,6 +4356,11 @@ define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-WMO-NEXT: .LBB31_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_acquire_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: amocas.d.aq a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
@@ -2913,6 +4371,11 @@ define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-TSO-NEXT: bnez a4, .LBB31_1
; RV64IA-TSO-NEXT: .LBB31_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_acquire_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire monotonic
ret void
}
@@ -2976,6 +4439,11 @@ define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-NEXT: .LBB32_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_acquire_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: amocas.d.aq a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
@@ -2986,6 +4454,11 @@ define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-NEXT: bnez a4, .LBB32_1
; RV64IA-TSO-NEXT: .LBB32_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_acquire_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire acquire
ret void
}
@@ -3049,6 +4522,11 @@ define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-WMO-NEXT: .LBB33_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_release_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: amocas.d.rl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
@@ -3059,6 +4537,11 @@ define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-TSO-NEXT: bnez a4, .LBB33_1
; RV64IA-TSO-NEXT: .LBB33_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_release_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release monotonic
ret void
}
@@ -3122,6 +4605,11 @@ define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-NEXT: .LBB34_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_release_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
@@ -3132,6 +4620,11 @@ define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-NEXT: bnez a4, .LBB34_1
; RV64IA-TSO-NEXT: .LBB34_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_release_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release acquire
ret void
}
@@ -3195,6 +4688,11 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-WMO-NEXT: .LBB35_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_acq_rel_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
@@ -3205,6 +4703,11 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-TSO-NEXT: bnez a4, .LBB35_1
; RV64IA-TSO-NEXT: .LBB35_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_acq_rel_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel monotonic
ret void
}
@@ -3268,6 +4771,11 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-NEXT: .LBB36_3:
; RV64IA-WMO-NEXT: ret
;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_acq_rel_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
@@ -3278,6 +4786,11 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-NEXT: bnez a4, .LBB36_1
; RV64IA-TSO-NEXT: .LBB36_3:
; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_acq_rel_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel acquire
ret void
}
@@ -3330,16 +4843,37 @@ define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i64_seq_cst_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.d.aqrl a3, (a0)
-; RV64IA-NEXT: bne a3, a1, .LBB37_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
-; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
-; RV64IA-NEXT: bnez a4, .LBB37_1
-; RV64IA-NEXT: .LBB37_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i64_seq_cst_monotonic:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.d.aqrl a3, (a0)
+; RV64IA-WMO-NEXT: bne a3, a1, .LBB37_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
+; RV64IA-WMO-NEXT: sc.d.rl a4, a2, (a0)
+; RV64IA-WMO-NEXT: bnez a4, .LBB37_1
+; RV64IA-WMO-NEXT: .LBB37_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_seq_cst_monotonic:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_monotonic:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.d.aqrl a3, (a0)
+; RV64IA-TSO-NEXT: bne a3, a1, .LBB37_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
+; RV64IA-TSO-NEXT: sc.d.rl a4, a2, (a0)
+; RV64IA-TSO-NEXT: bnez a4, .LBB37_1
+; RV64IA-TSO-NEXT: .LBB37_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_seq_cst_monotonic:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst monotonic
ret void
}
@@ -3392,16 +4926,37 @@ define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i64_seq_cst_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.d.aqrl a3, (a0)
-; RV64IA-NEXT: bne a3, a1, .LBB38_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
-; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
-; RV64IA-NEXT: bnez a4, .LBB38_1
-; RV64IA-NEXT: .LBB38_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i64_seq_cst_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.d.aqrl a3, (a0)
+; RV64IA-WMO-NEXT: bne a3, a1, .LBB38_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
+; RV64IA-WMO-NEXT: sc.d.rl a4, a2, (a0)
+; RV64IA-WMO-NEXT: bnez a4, .LBB38_1
+; RV64IA-WMO-NEXT: .LBB38_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_seq_cst_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.d.aqrl a3, (a0)
+; RV64IA-TSO-NEXT: bne a3, a1, .LBB38_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
+; RV64IA-TSO-NEXT: sc.d.rl a4, a2, (a0)
+; RV64IA-TSO-NEXT: bnez a4, .LBB38_1
+; RV64IA-TSO-NEXT: .LBB38_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_seq_cst_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst acquire
ret void
}
@@ -3454,16 +5009,37 @@ define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.d.aqrl a3, (a0)
-; RV64IA-NEXT: bne a3, a1, .LBB39_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
-; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
-; RV64IA-NEXT: bnez a4, .LBB39_1
-; RV64IA-NEXT: .LBB39_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i64_seq_cst_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.d.aqrl a3, (a0)
+; RV64IA-WMO-NEXT: bne a3, a1, .LBB39_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
+; RV64IA-WMO-NEXT: sc.d.rl a4, a2, (a0)
+; RV64IA-WMO-NEXT: bnez a4, .LBB39_1
+; RV64IA-WMO-NEXT: .LBB39_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: cmpxchg_i64_seq_cst_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.d.aqrl a3, (a0)
+; RV64IA-TSO-NEXT: bne a3, a1, .LBB39_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
+; RV64IA-TSO-NEXT: sc.d.rl a4, a2, (a0)
+; RV64IA-TSO-NEXT: bnez a4, .LBB39_1
+; RV64IA-TSO-NEXT: .LBB39_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: cmpxchg_i64_seq_cst_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZACAS-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst seq_cst
ret void
}
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