[llvm] [MacroFusion] Add IsPostRA to indicate whether running in post-ra scheduler (PR #77567)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 10 09:24:50 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/77567
>From 8a038f5e2737314046f1b9c1105f6bda1b5e3274 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Wed, 10 Jan 2024 14:57:43 +0800
Subject: [PATCH] [MacroFusion] Add IsPostRA to MacroFusionPredTy
This can save some time to know whether MacroFusion mutation is
running in post-ra scheduler.
And this can be used in #77461.
---
llvm/include/llvm/CodeGen/MacroFusion.h | 2 +-
llvm/include/llvm/Target/TargetSchedule.td | 15 +++---
llvm/lib/CodeGen/MacroFusion.cpp | 13 +++--
.../lib/Target/AArch64/AArch64MacroFusion.cpp | 3 +-
llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp | 3 +-
llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp | 7 +--
llvm/lib/Target/ARM/ARMMacroFusion.cpp | 3 +-
llvm/lib/Target/PowerPC/PPCMacroFusion.cpp | 3 +-
llvm/lib/Target/RISCV/RISCVMacroFusion.cpp | 49 ++++++++++---------
llvm/lib/Target/X86/X86MacroFusion.cpp | 3 +-
llvm/test/TableGen/MacroFusion.td | 22 +++------
.../TableGen/MacroFusionPredicatorEmitter.cpp | 21 ++++----
12 files changed, 78 insertions(+), 66 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MacroFusion.h b/llvm/include/llvm/CodeGen/MacroFusion.h
index 191c906e9ef6c6..58d1784435a3ca 100644
--- a/llvm/include/llvm/CodeGen/MacroFusion.h
+++ b/llvm/include/llvm/CodeGen/MacroFusion.h
@@ -32,7 +32,7 @@ class SUnit;
using MacroFusionPredTy = bool (*)(const TargetInstrInfo &TII,
const TargetSubtargetInfo &STI,
const MachineInstr *FirstMI,
- const MachineInstr &SecondMI);
+ const MachineInstr &SecondMI, bool IsPostRA);
/// Checks if the number of cluster edges between SU and its predecessors is
/// less than FuseLimit
diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td
index 2016d452afb6f3..b317cd129bc6e6 100644
--- a/llvm/include/llvm/Target/TargetSchedule.td
+++ b/llvm/include/llvm/Target/TargetSchedule.td
@@ -597,6 +597,7 @@ def both_fusion_target : FusionTarget;
// * const MachineRegisterInfo &MRI
// * const MachineInstr *FirstMI
// * const MachineInstr &SecondMI
+// * bool IsPostRA
class FusionPredicate<FusionTarget target> {
FusionTarget Target = target;
}
@@ -642,10 +643,16 @@ def WildcardFalse : WildcardPred<0>;
def WildcardTrue : WildcardPred<1>;
// Indicates that the destination register of `FirstMI` should have one use if
-// it is a virtual register.
+// it is a virtual register (fusion is done in pre-ra scheduler).
class OneUsePred : FirstFusionPredicate;
def OneUse : OneUsePred;
+// Indicates that the first register of `SecondMI` should be the same as the
+// second register if it is a physical register (fusion is done in post-ra
+// scheduler).
+class SameRegisterPred : SecondFusionPredicate;
+def SameRegister : SameRegisterPred;
+
// Handled by MacroFusionPredicatorEmitter backend.
// The generated predicator will be like:
// ```
@@ -688,11 +695,7 @@ class SimpleFusion<MCInstPredicate firstPred, MCInstPredicate secondPred,
SecondFusionPredicateWithMCInstPredicate<secondPred>,
WildcardTrue,
FirstFusionPredicateWithMCInstPredicate<firstPred>,
- SecondFusionPredicateWithMCInstPredicate<
- CheckAny<[
- CheckIsVRegOperand<0>,
- CheckSameRegOperand<0, 1>
- ]>>,
+ SameRegister,
OneUse,
TieReg<0, 1>,
],
diff --git a/llvm/lib/CodeGen/MacroFusion.cpp b/llvm/lib/CodeGen/MacroFusion.cpp
index 5bd6ca0978a4b1..e8ed35e6bcced5 100644
--- a/llvm/lib/CodeGen/MacroFusion.cpp
+++ b/llvm/lib/CodeGen/MacroFusion.cpp
@@ -151,7 +151,7 @@ class MacroFusion : public ScheduleDAGMutation {
bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
const TargetSubtargetInfo &STI,
const MachineInstr *FirstMI,
- const MachineInstr &SecondMI);
+ const MachineInstr &SecondMI, bool IsPostRA);
};
} // end anonymous namespace
@@ -159,9 +159,10 @@ class MacroFusion : public ScheduleDAGMutation {
bool MacroFusion::shouldScheduleAdjacent(const TargetInstrInfo &TII,
const TargetSubtargetInfo &STI,
const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
+ const MachineInstr &SecondMI,
+ bool IsPostRA) {
return llvm::any_of(Predicates, [&](MacroFusionPredTy Predicate) {
- return Predicate(TII, STI, FirstMI, SecondMI);
+ return Predicate(TII, STI, FirstMI, SecondMI, IsPostRA);
});
}
@@ -183,9 +184,11 @@ bool MacroFusion::scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU)
const MachineInstr &AnchorMI = *AnchorSU.getInstr();
const TargetInstrInfo &TII = *DAG.TII;
const TargetSubtargetInfo &ST = DAG.MF.getSubtarget();
+ bool IsPostRA = DAG.MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::NoVRegs);
// Check if the anchor instr may be fused.
- if (!shouldScheduleAdjacent(TII, ST, nullptr, AnchorMI))
+ if (!shouldScheduleAdjacent(TII, ST, nullptr, AnchorMI, IsPostRA))
return false;
// Explorer for fusion candidates among the dependencies of the anchor instr.
@@ -201,7 +204,7 @@ bool MacroFusion::scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU)
// Only chain two instructions together at most.
const MachineInstr *DepMI = DepSU.getInstr();
if (!hasLessThanNumFused(DepSU, 2) ||
- !shouldScheduleAdjacent(TII, ST, DepMI, AnchorMI))
+ !shouldScheduleAdjacent(TII, ST, DepMI, AnchorMI, IsPostRA))
continue;
if (fuseInstructionPair(DAG, DepSU, AnchorSU))
diff --git a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
index 05d60872bf51ac..d987d44f9fb5fc 100644
--- a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
@@ -443,7 +443,8 @@ static bool isAddSub2RegAndConstOnePair(const MachineInstr *FirstMI,
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
const TargetSubtargetInfo &TSI,
const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
+ const MachineInstr &SecondMI,
+ bool IsPostRA) {
const AArch64Subtarget &ST = static_cast<const AArch64Subtarget&>(TSI);
// All checking functions assume that the 1st instr is a wildcard if it is
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
index 0cbabf3895a67e..8b93a417fb30f2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
@@ -26,7 +26,8 @@ namespace {
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII_,
const TargetSubtargetInfo &TSI,
const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
+ const MachineInstr &SecondMI,
+ bool IsPostRA) {
const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_);
switch (SecondMI.getOpcode()) {
diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
index 33c208495c500e..6328edd70feede 100644
--- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
@@ -123,7 +123,8 @@ bool llvm::checkVOPDRegConstraints(const SIInstrInfo &TII,
static bool shouldScheduleVOPDAdjacent(const TargetInstrInfo &TII,
const TargetSubtargetInfo &TSI,
const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
+ const MachineInstr &SecondMI,
+ bool IsPostRA) {
const SIInstrInfo &STII = static_cast<const SIInstrInfo &>(TII);
unsigned Opc2 = SecondMI.getOpcode();
auto SecondCanBeVOPD = AMDGPU::getCanBeVOPD(Opc2);
@@ -165,7 +166,7 @@ struct VOPDPairingMutation : ScheduleDAGMutation {
std::vector<SUnit>::iterator ISUI, JSUI;
for (ISUI = DAG->SUnits.begin(); ISUI != DAG->SUnits.end(); ++ISUI) {
const MachineInstr *IMI = ISUI->getInstr();
- if (!shouldScheduleAdjacent(TII, ST, nullptr, *IMI))
+ if (!shouldScheduleAdjacent(TII, ST, nullptr, *IMI, /*IsPostRA=*/true))
continue;
if (!hasLessThanNumFused(*ISUI, 2))
continue;
@@ -175,7 +176,7 @@ struct VOPDPairingMutation : ScheduleDAGMutation {
continue;
const MachineInstr *JMI = JSUI->getInstr();
if (!hasLessThanNumFused(*JSUI, 2) ||
- !shouldScheduleAdjacent(TII, ST, IMI, *JMI))
+ !shouldScheduleAdjacent(TII, ST, IMI, *JMI, /*IsPostRA=*/true))
continue;
if (fuseInstructionPair(*DAG, *ISUI, *JSUI))
break;
diff --git a/llvm/lib/Target/ARM/ARMMacroFusion.cpp b/llvm/lib/Target/ARM/ARMMacroFusion.cpp
index 5aeb7abe92a38c..752e3705bf270b 100644
--- a/llvm/lib/Target/ARM/ARMMacroFusion.cpp
+++ b/llvm/lib/Target/ARM/ARMMacroFusion.cpp
@@ -51,7 +51,8 @@ static bool isLiteralsPair(const MachineInstr *FirstMI,
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
const TargetSubtargetInfo &TSI,
const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
+ const MachineInstr &SecondMI,
+ bool IsPostRA) {
const ARMSubtarget &ST = static_cast<const ARMSubtarget&>(TSI);
if (ST.hasFuseAES() && isAESPair(FirstMI, SecondMI))
diff --git a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
index 7ad6ef8c39286d..65677792edd278 100644
--- a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
@@ -234,7 +234,8 @@ static bool checkOpConstraints(FusionFeature::FusionKind Kd,
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
const TargetSubtargetInfo &TSI,
const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
+ const MachineInstr &SecondMI,
+ bool IsPostRA) {
// We use the PPC namespace to avoid the need to prefix opcodes with PPC:: in
// the def file.
using namespace PPC;
diff --git a/llvm/lib/Target/RISCV/RISCVMacroFusion.cpp b/llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
index f948f05b22f772..5d9f694325a421 100644
--- a/llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
@@ -18,7 +18,8 @@
using namespace llvm;
-static bool checkRegisters(Register FirstDest, const MachineInstr &SecondMI) {
+static bool checkRegisters(Register FirstDest, const MachineInstr &SecondMI,
+ bool IsPostRA) {
if (!SecondMI.getOperand(1).isReg())
return false;
@@ -26,7 +27,7 @@ static bool checkRegisters(Register FirstDest, const MachineInstr &SecondMI) {
return false;
// If the input is virtual make sure this is the only user.
- if (FirstDest.isVirtual()) {
+ if (!IsPostRA) {
auto &MRI = SecondMI.getMF()->getRegInfo();
return MRI.hasOneNonDBGUse(FirstDest);
}
@@ -37,7 +38,8 @@ static bool checkRegisters(Register FirstDest, const MachineInstr &SecondMI) {
// Fuse load with add:
// add rd, rs1, rs2
// ld rd, 0(rd)
-static bool isLDADD(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
+static bool isLDADD(const MachineInstr *FirstMI, const MachineInstr &SecondMI,
+ bool IsPostRA) {
if (SecondMI.getOpcode() != RISCV::LD)
return false;
@@ -55,13 +57,14 @@ static bool isLDADD(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
if (FirstMI->getOpcode() != RISCV::ADD)
return true;
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
+ return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI, IsPostRA);
}
// Fuse zero extension of halfword:
// slli rd, rs1, 48
// srli rd, rd, 48
-static bool isZExtH(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
+static bool isZExtH(const MachineInstr *FirstMI, const MachineInstr &SecondMI,
+ bool IsPostRA) {
if (SecondMI.getOpcode() != RISCV::SRLI)
return false;
@@ -82,13 +85,14 @@ static bool isZExtH(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
if (FirstMI->getOperand(2).getImm() != 48)
return false;
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
+ return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI, IsPostRA);
}
// Fuse zero extension of word:
// slli rd, rs1, 32
// srli rd, rd, 32
-static bool isZExtW(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
+static bool isZExtW(const MachineInstr *FirstMI, const MachineInstr &SecondMI,
+ bool IsPostRA) {
if (SecondMI.getOpcode() != RISCV::SRLI)
return false;
@@ -109,7 +113,7 @@ static bool isZExtW(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
if (FirstMI->getOperand(2).getImm() != 32)
return false;
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
+ return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI, IsPostRA);
}
// Fuse shifted zero extension of word:
@@ -117,7 +121,7 @@ static bool isZExtW(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
// srli rd, rd, x
// where 0 <= x < 32
static bool isShiftedZExtW(const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
+ const MachineInstr &SecondMI, bool IsPostRA) {
if (SecondMI.getOpcode() != RISCV::SRLI)
return false;
@@ -139,14 +143,14 @@ static bool isShiftedZExtW(const MachineInstr *FirstMI,
if (FirstMI->getOperand(2).getImm() != 32)
return false;
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
+ return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI, IsPostRA);
}
// Fuse AUIPC followed by ADDI
// auipc rd, imm20
// addi rd, rd, imm12
static bool isAUIPCADDI(const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
+ const MachineInstr &SecondMI, bool IsPostRA) {
if (SecondMI.getOpcode() != RISCV::ADDI)
return false;
// Assume the 1st instr to be a wildcard if it is unspecified.
@@ -156,15 +160,15 @@ static bool isAUIPCADDI(const MachineInstr *FirstMI,
if (FirstMI->getOpcode() != RISCV::AUIPC)
return false;
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
+ return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI, IsPostRA);
}
// Fuse LUI followed by ADDI or ADDIW.
// rd = imm[31:0] which decomposes to
// lui rd, imm[31:12]
// addi(w) rd, rd, imm[11:0]
-static bool isLUIADDI(const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
+static bool isLUIADDI(const MachineInstr *FirstMI, const MachineInstr &SecondMI,
+ bool IsPostRA) {
if (SecondMI.getOpcode() != RISCV::ADDI &&
SecondMI.getOpcode() != RISCV::ADDIW)
return false;
@@ -175,31 +179,32 @@ static bool isLUIADDI(const MachineInstr *FirstMI,
if (FirstMI->getOpcode() != RISCV::LUI)
return false;
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
+ return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI, IsPostRA);
}
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
const TargetSubtargetInfo &TSI,
const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
+ const MachineInstr &SecondMI,
+ bool IsPostRA) {
const RISCVSubtarget &ST = static_cast<const RISCVSubtarget &>(TSI);
- if (ST.hasLUIADDIFusion() && isLUIADDI(FirstMI, SecondMI))
+ if (ST.hasLUIADDIFusion() && isLUIADDI(FirstMI, SecondMI, IsPostRA))
return true;
- if (ST.hasAUIPCADDIFusion() && isAUIPCADDI(FirstMI, SecondMI))
+ if (ST.hasAUIPCADDIFusion() && isAUIPCADDI(FirstMI, SecondMI, IsPostRA))
return true;
- if (ST.hasZExtHFusion() && isZExtH(FirstMI, SecondMI))
+ if (ST.hasZExtHFusion() && isZExtH(FirstMI, SecondMI, IsPostRA))
return true;
- if (ST.hasZExtWFusion() && isZExtW(FirstMI, SecondMI))
+ if (ST.hasZExtWFusion() && isZExtW(FirstMI, SecondMI, IsPostRA))
return true;
- if (ST.hasShiftedZExtWFusion() && isShiftedZExtW(FirstMI, SecondMI))
+ if (ST.hasShiftedZExtWFusion() && isShiftedZExtW(FirstMI, SecondMI, IsPostRA))
return true;
- if (ST.hasLDADDFusion() && isLDADD(FirstMI, SecondMI))
+ if (ST.hasLDADDFusion() && isLDADD(FirstMI, SecondMI, IsPostRA))
return true;
return false;
diff --git a/llvm/lib/Target/X86/X86MacroFusion.cpp b/llvm/lib/Target/X86/X86MacroFusion.cpp
index c0fa9aa7032437..cd0f7c04443e8d 100644
--- a/llvm/lib/Target/X86/X86MacroFusion.cpp
+++ b/llvm/lib/Target/X86/X86MacroFusion.cpp
@@ -35,7 +35,8 @@ static X86::SecondMacroFusionInstKind classifySecond(const MachineInstr &MI) {
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
const TargetSubtargetInfo &TSI,
const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
+ const MachineInstr &SecondMI,
+ bool IsPostRA) {
const X86Subtarget &ST = static_cast<const X86Subtarget &>(TSI);
// Check if this processor supports any kind of fusion.
diff --git a/llvm/test/TableGen/MacroFusion.td b/llvm/test/TableGen/MacroFusion.td
index f984a142839c95..5ad021ae3e171e 100644
--- a/llvm/test/TableGen/MacroFusion.td
+++ b/llvm/test/TableGen/MacroFusion.td
@@ -43,7 +43,7 @@ def TestFusion: SimpleFusion<CheckOpcode<[Inst0]>,
// CHECK-PREDICATOR-NEXT: #undef GET_Test_MACRO_FUSION_PRED_DECL
// CHECK-PREDICATOR-EMPTY:
// CHECK-PREDICATOR-NEXT: namespace llvm {
-// CHECK-PREDICATOR-NEXT: bool isTestFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
+// CHECK-PREDICATOR-NEXT: bool isTestFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &, bool);
// CHECK-PREDICATOR-NEXT: } // end namespace llvm
// CHECK-PREDICATOR-EMPTY:
// CHECK-PREDICATOR-NEXT: #endif
@@ -56,7 +56,8 @@ def TestFusion: SimpleFusion<CheckOpcode<[Inst0]>,
// CHECK-PREDICATOR-NEXT: const TargetInstrInfo &TII,
// CHECK-PREDICATOR-NEXT: const TargetSubtargetInfo &STI,
// CHECK-PREDICATOR-NEXT: const MachineInstr *FirstMI,
-// CHECK-PREDICATOR-NEXT: const MachineInstr &SecondMI) {
+// CHECK-PREDICATOR-NEXT: const MachineInstr &SecondMI,
+// CHECK-PREDICATOR-NEXT: bool IsPostRA) {
// CHECK-PREDICATOR-NEXT: auto &MRI = SecondMI.getMF()->getRegInfo();
// CHECK-PREDICATOR-NEXT: {
// CHECK-PREDICATOR-NEXT: const MachineInstr *MI = &SecondMI;
@@ -73,19 +74,10 @@ def TestFusion: SimpleFusion<CheckOpcode<[Inst0]>,
// CHECK-PREDICATOR-NEXT: if (( MI->getOpcode() != Test::Inst0 ))
// CHECK-PREDICATOR-NEXT: return false;
// CHECK-PREDICATOR-NEXT: }
-// CHECK-PREDICATOR-NEXT: {
-// CHECK-PREDICATOR-NEXT: const MachineInstr *MI = &SecondMI;
-// CHECK-PREDICATOR-NEXT: if (!(
-// CHECK-PREDICATOR-NEXT: MI->getOperand(0).getReg().isVirtual()
-// CHECK-PREDICATOR-NEXT: || MI->getOperand(0).getReg() == MI->getOperand(1).getReg()
-// CHECK-PREDICATOR-NEXT: ))
-// CHECK-PREDICATOR-NEXT: return false;
-// CHECK-PREDICATOR-NEXT: }
-// CHECK-PREDICATOR-NEXT: {
-// CHECK-PREDICATOR-NEXT: Register FirstDest = FirstMI->getOperand(0).getReg();
-// CHECK-PREDICATOR-NEXT: if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
-// CHECK-PREDICATOR-NEXT: return false;
-// CHECK-PREDICATOR-NEXT: }
+// CHECK-PREDICATOR-NEXT: if (IsPostRA && SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg())
+// CHECK-PREDICATOR-NEXT: return false;
+// CHECK-PREDICATOR-NEXT: if (!IsPostRA && !MRI.hasOneNonDBGUse(FirstMI->getOperand(0).getReg()))
+// CHECK-PREDICATOR-NEXT: return false;
// CHECK-PREDICATOR-NEXT: if (!(FirstMI->getOperand(0).isReg() &&
// CHECK-PREDICATOR-NEXT: SecondMI.getOperand(1).isReg() &&
// CHECK-PREDICATOR-NEXT: FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
diff --git a/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp b/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
index 78dcd4471ae747..dbaa662adc39c3 100644
--- a/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
+++ b/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
@@ -25,7 +25,8 @@
// bool isNAME(const TargetInstrInfo &TII,
// const TargetSubtargetInfo &STI,
// const MachineInstr *FirstMI,
-// const MachineInstr &SecondMI) {
+// const MachineInstr &SecondMI,
+// bool IsPostRA) {
// auto &MRI = SecondMI.getMF()->getRegInfo();
// /* Predicates */
// return true;
@@ -87,7 +88,7 @@ void MacroFusionPredicatorEmitter::emitMacroFusionDecl(
OS << "bool is" << Fusion->getName() << "(const TargetInstrInfo &, "
<< "const TargetSubtargetInfo &, "
<< "const MachineInstr *, "
- << "const MachineInstr &);\n";
+ << "const MachineInstr &, bool);\n";
}
OS << "} // end namespace llvm\n";
@@ -108,7 +109,8 @@ void MacroFusionPredicatorEmitter::emitMacroFusionImpl(
OS.indent(4) << "const TargetInstrInfo &TII,\n";
OS.indent(4) << "const TargetSubtargetInfo &STI,\n";
OS.indent(4) << "const MachineInstr *FirstMI,\n";
- OS.indent(4) << "const MachineInstr &SecondMI) {\n";
+ OS.indent(4) << "const MachineInstr &SecondMI,\n";
+ OS.indent(4) << "bool IsPostRA) {\n";
OS.indent(2) << "auto &MRI = SecondMI.getMF()->getRegInfo();\n";
emitPredicates(Predicates, PE, OS);
@@ -146,12 +148,9 @@ void MacroFusionPredicatorEmitter::emitFirstPredicate(Record *Predicate,
<< (Predicate->getValueAsBit("ReturnValue") ? "true" : "false")
<< ";\n";
} else if (Predicate->isSubClassOf("OneUsePred")) {
- OS.indent(2) << "{\n";
- OS.indent(4) << "Register FirstDest = FirstMI->getOperand(0).getReg();\n";
- OS.indent(4)
- << "if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))\n";
- OS.indent(4) << " return false;\n";
- OS.indent(2) << "}\n";
+ OS.indent(2) << "if (!IsPostRA && "
+ "!MRI.hasOneNonDBGUse(FirstMI->getOperand(0).getReg()))\n";
+ OS.indent(2) << " return false;\n";
} else if (Predicate->isSubClassOf(
"FirstFusionPredicateWithMCInstPredicate")) {
OS.indent(2) << "{\n";
@@ -183,6 +182,10 @@ void MacroFusionPredicatorEmitter::emitSecondPredicate(Record *Predicate,
OS << ")\n";
OS.indent(4) << " return false;\n";
OS.indent(2) << "}\n";
+ } else if (Predicate->isSubClassOf("SameRegisterPred")) {
+ OS.indent(3) << "if (IsPostRA && SecondMI.getOperand(0).getReg() != "
+ "SecondMI.getOperand(1).getReg())\n";
+ OS.indent(2) << " return false;\n";
} else {
PrintFatalError(Predicate->getLoc(),
"Unsupported predicate for first instruction: " +
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