[llvm] [CodeGen][X86] Fix lowering of tailcalls when `-ms-hotpatch` is used (PR #77245)

[via llvm-commits]

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@@ -948,24 +948,26 @@ void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
 
 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
                                       X86MCInstLower &MCIL) {
-  // PATCHABLE_OP minsize, opcode, operands
+  // PATCHABLE_OP minsize
 
   NoAutoPaddingScope NoPadScope(*OutStreamer);
 
-  unsigned MinSize = MI.getOperand(0).getImm();
-  unsigned Opcode = MI.getOperand(1).getImm();
-  // Opcode PATCHABLE_OP is a special case: there is no instruction to wrap,
-  // simply emit a nop of size MinSize.
-  bool EmptyInst = (Opcode == TargetOpcode::PATCHABLE_OP);
-
-  MCInst MCI;
-  MCI.setOpcode(Opcode);
-  for (auto &MO : drop_begin(MI.operands(), 2))
-    if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
-      MCI.addOperand(*MaybeOperand);
+  // Find the next MachineInstr in this MBB.
+  const MachineInstr *NextMI = MI.getNextNode();
+  while (NextMI) {
+    if (!NextMI->isMetaInstruction())
+      break;
+    NextMI = NextMI->getNextNode();
+  }
 
   SmallString<256> Code;
-  if (!EmptyInst) {
+  unsigned MinSize = MI.getOperand(0).getImm();
+
+  if (NextMI) {
+    // Lower the next MachineInstr to find its byte size.
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sylvain-audi wrote:

Would it be possible here to use `X86AsmPrinter`'s `emitInstruction` to lower `NextMI`?
That way it should guarantee we match what will be generated when handling the next `MachineInstr`.
But I don't know how feasible it is, as it may have some edge effects...


https://github.com/llvm/llvm-project/pull/77245