[llvm] [AArch64] MI Scheduler: create more LDP/STP pairs (PR #77565)

[Sjoerd Meijer via llvm-commits]

sjoerdmeijer wrote:

> Yeah I think there will always be a limit to what the load-store optimizer can figure out, and this is just adding a few more LDRQ<->LDURQ and LDURQ<->LDRQ pairings to what we already do.
> 
> Is it worth extending that to LDRS and LDRD to fill in the gaps?

Yeah, I forgot to mention this. This is actually fixing a regression when we moved from the N2 to the V2 scheduling model. I wanted to test the water and fix the regression first, then follow up to handle a few more cases. Writing the other test cases is slightly tricky because to prove the point registers need to be reused; but wanted to do this in a follow up.

https://github.com/llvm/llvm-project/pull/77565