[llvm] [X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (PR #77564)

[Phoebe Wang via llvm-commits]

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@@ -1107,43 +1107,85 @@ def : Pat<(store (X86adc_flag GR64:$src, (loadi64 addr:$dst), EFLAGS),
 
 // Patterns for basic arithmetic ops with relocImm for the immediate field.
 multiclass ArithBinOp_RF_relocImm_Pats<SDNode OpNodeFlag, SDNode OpNode> {
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phoebewang wrote:

Why do we need to define these patterns again given we defined during defining the instruction?

https://github.com/llvm/llvm-project/pull/77564