[llvm] [X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (PR #77564)

[Phoebe Wang via llvm-commits]

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@@ -1107,43 +1107,85 @@ def : Pat<(store (X86adc_flag GR64:$src, (loadi64 addr:$dst), EFLAGS),
 
 // Patterns for basic arithmetic ops with relocImm for the immediate field.
 multiclass ArithBinOp_RF_relocImm_Pats<SDNode OpNodeFlag, SDNode OpNode> {
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phoebewang wrote:

Maybe split it into 2 multiclass, e.g.,
```
multiclass ArithBinOp_RF_relocImm_Pats_All<SDNode OpNodeFlag, SDNode OpNode> {
  defm : ArithBinOp_RF_relocImm_Pats<OpNodeFlag, OpNode, 0>,  ArithBinOp_RF_relocImm_Pats<OpNodeFlag, OpNode, 1>;
}
multiclass ArithBinOp_RF_relocImm_Pats<SDNode OpNodeFlag, SDNode OpNode, bit ndd> {
  let Predicates = !if(!eq(ndd, 0), [NoNDD], [HasNDD]) in {
    def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2),
              (!cast<Instruction>(NAME#"8ri"#!if(!eq(ndd, 0), "", "_ND")) GR8:$src1, relocImm8_su:$src2)>;
  }
}
```
just add a `bit ndd` argument and then

https://github.com/llvm/llvm-project/pull/77564