[llvm] [RISCV] Allow VCIX with SE to reorder (PR #77049)

[Craig Topper via llvm-commits]

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@@ -8832,72 +8901,117 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
         FixedIntrinsic->getMemoryVT(), FixedIntrinsic->getMemOperand());
   }
   case Intrinsic::riscv_sf_vc_x_se_e8mf8:
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topperc wrote:

Would it be possible to redefine riscv_sf_vc_x_se* and riscv_sf_vc_i_se IR intrinsics store the sew and lmul as immediate operands like vsetvli. Then use those immediate operands during isel to select the instructions? That would remove 42 intrinsics I think.

https://github.com/llvm/llvm-project/pull/77049