[llvm] 6615581 - [PowerPC] Make verifier happy when lowering `llvm.trap` (#77266)

[via llvm-commits]

Author: Kai Luo
Date: 2024-01-10T09:23:30+08:00
New Revision: 6615581526f62a00833b2d60cc31f7f12497b5ff

URL: https://github.com/llvm/llvm-project/commit/6615581526f62a00833b2d60cc31f7f12497b5ff
DIFF: https://github.com/llvm/llvm-project/commit/6615581526f62a00833b2d60cc31f7f12497b5ff.diff

LOG: [PowerPC] Make verifier happy when lowering `llvm.trap` (#77266)

`llvm.trap` is lowered to `PPC::TRAP` and `PPC::TRAP` is set as
terminator. Verifier complains about terminator should not lie in the
middle of an MBB. See #77095.

Fix it by removing `isTerminator` and `isBarrier` and then set `isTrap`
which was introduced by https://reviews.llvm.org/D48836# and is being
used by X86 and AArch64.

`PPC::TRAP` is not a hardware memory barrier and `llvm.trap` doesn't
indicate a memory barrier either.

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrInfo.td
    llvm/test/CodeGen/PowerPC/intrinsic-trap.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index b1601739fd4569..bf756e39bd5d07 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1909,7 +1909,7 @@ def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB),
                           "stwat $RST, $RA, $RB", IIC_LdStStore>,
             Requires<[IsISA3_0]>;
 
-let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isTrap = 1, hasCtrlDep = 1 in
 def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
 
 def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops),

diff  --git a/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll b/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll
index b02eb5d8fd27a7..b8eb7a35f61e17 100644
--- a/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll
+++ b/llvm/test/CodeGen/PowerPC/intrinsic-trap.ll
@@ -1,8 +1,14 @@
-; REQUIRES: asserts
-; RUN: not --crash llc -verify-machineinstrs -mtriple=powerpc64le-- < %s 2>&1 | FileCheck %s
-; CHECK: Bad machine code: Non-terminator instruction after the first terminator
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -ppc-opt-conditional-trap \
+; RUN:   < %s | FileCheck %s
 
 define i32 @test() {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    trap
+; CHECK-NEXT:    blr
   call void @llvm.trap()
   ret i32 0
 }