[llvm] [SVE] Wide active lane mask (PR #76514)

[via llvm-commits]

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@@ -19791,15 +19792,63 @@ static SDValue performIntrinsicCombine(SDNode *N,
           EVT::getVectorVT(*DAG.getContext(), PromVT.getVectorElementType(),
                            VT.getVectorElementCount());
 
-      Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, WhileVT, ID,
-                        N->getOperand(1), N->getOperand(2));
+      SDValue Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, WhileVT, ID,
+                                N->getOperand(1), N->getOperand(2));
       Res = DAG.getNode(ISD::SIGN_EXTEND, DL, PromVT, Res);
       Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtVT, Res,
                         DAG.getConstant(0, DL, MVT::i64));
       Res = DAG.getNode(ISD::TRUNCATE, DL, VT, Res);
+
+      return Res;
     }
-    return Res;
+
+    if (!Subtarget->hasSVE2p1() && !Subtarget->hasSME2())
+      return SDValue();
+
+    if (!N->hasNUsesOfValue(2, 0))
+      return SDValue();
+
+    auto It = N->use_begin();
+    SDNode *Lo = *It++;
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CarolineConcatto wrote:

That is part of DAG output.
  t6: nxv32i1 = llvm.get.active.lane.mask TargetConstant:i64<167>, t2, t4
    t8: nxv16i1 = extract_subvector t6, Constant:i64<0>
  t12: ch,glue = CopyToReg t0, Register:nxv16i1 $p0, t8
    t10: nxv16i1 = extract_subvector t6, Constant:i64<16>
AFAIU the first extract has offset 0 and the second  has offset 16. I believe it will always be in that order, as this probably will be a for loop starting from 0


https://github.com/llvm/llvm-project/pull/76514