[llvm] 0b9b00c - [AMDGPU] Make isScalarLoadLegal a member of AMDGPURegisterBankInfo. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2024-01-09T11:53:12Z
New Revision: 0b9b00c8c86d42f72f8abf379052a451778dcc63

URL: https://github.com/llvm/llvm-project/commit/0b9b00c8c86d42f72f8abf379052a451778dcc63
DIFF: https://github.com/llvm/llvm-project/commit/0b9b00c8c86d42f72f8abf379052a451778dcc63.diff

LOG: [AMDGPU] Make isScalarLoadLegal a member of AMDGPURegisterBankInfo. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index ecb7bb9d1d9755..391c2b9ec256ea 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -441,7 +441,7 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects(
 
 // FIXME: Returns uniform if there's no source value information. This is
 // probably wrong.
-static bool isScalarLoadLegal(const MachineInstr &MI) {
+bool AMDGPURegisterBankInfo::isScalarLoadLegal(const MachineInstr &MI) const {
   if (!MI.hasOneMemOperand())
     return false;
 

diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
index 2bb5ef57fe0314..5f550b426ec093 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
@@ -176,6 +176,8 @@ class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo {
   const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
                                              LLT) const override;
 
+  bool isScalarLoadLegal(const MachineInstr &MI) const;
+
   InstructionMappings
   getInstrAlternativeMappings(const MachineInstr &MI) const override;