[llvm] [MC] Add support for `exclude` flag when parsing sun-style section flags (PR #77267)
Shilei Tian via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 8 19:54:51 PST 2024
https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/77267
>From ebfe7064963fa24a5acda392a8723ba0524e3a35 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Mon, 8 Jan 2024 22:54:38 -0500
Subject: [PATCH] [MC] Add support for `exclude` flag when parsing sun-style
section flags
Fix #64862.
---
.../Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp | 1 -
llvm/test/CodeGen/AMDGPU/code-object-v3.ll | 4 ++--
llvm/test/CodeGen/AMDGPU/hsa-globals.ll | 2 +-
.../CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll | 2 +-
.../CodeGen/AMDGPU/lower-module-lds-via-table.ll | 2 +-
llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll | 12 ++++++------
llvm/test/MC/AsmParser/pr64862.s | 4 ++++
7 files changed, 15 insertions(+), 12 deletions(-)
create mode 100644 llvm/test/MC/AsmParser/pr64862.s
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
index d539d75fdff065..201cc8d01e2d4b 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
@@ -31,7 +31,6 @@ AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
InlineAsmEnd = ";#ASMEND";
//===--- Data Emission Directives -------------------------------------===//
- SunStyleELFSectionSwitchSyntax = true;
UsesELFSectionDirectiveForBSS = true;
//===--- Global Variable Emission Directives --------------------------===//
diff --git a/llvm/test/CodeGen/AMDGPU/code-object-v3.ll b/llvm/test/CodeGen/AMDGPU/code-object-v3.ll
index 1db0f29ed74a14..9321bc262c4a49 100644
--- a/llvm/test/CodeGen/AMDGPU/code-object-v3.ll
+++ b/llvm/test/CodeGen/AMDGPU/code-object-v3.ll
@@ -9,7 +9,7 @@
; OSABI-AMDHSA-ASM-NOT: .amd_kernel_code_t
; OSABI-AMDHSA-ASM: s_endpgm
-; OSABI-AMDHSA-ASM: .section .rodata,#alloc
+; OSABI-AMDHSA-ASM: .section .rodata,"a"
; OSABI-AMDHSA-ASM: .p2align 6
; OSABI-AMDHSA-ASM: .amdhsa_kernel fadd
; OSABI-AMDHSA-ASM: .amdhsa_user_sgpr_count 6
@@ -28,7 +28,7 @@
; OSABI-AMDHSA-ASM-NOT: .amd_kernel_code_t
; OSABI-AMDHSA-ASM: s_endpgm
-; OSABI-AMDHSA-ASM: .section .rodata,#alloc
+; OSABI-AMDHSA-ASM: .section .rodata,"a"
; OSABI-AMDHSA-ASM: .p2align 6
; OSABI-AMDHSA-ASM: .amdhsa_kernel fsub
; OSABI-AMDHSA-ASM: .amdhsa_user_sgpr_count 6
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-globals.ll b/llvm/test/CodeGen/AMDGPU/hsa-globals.ll
index bbb96072dfaf5f..dc74505e34feeb 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-globals.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-globals.ll
@@ -16,7 +16,7 @@ define amdgpu_kernel void @test() {
@weak_global = extern_weak addrspace(1) global i32
; ASM: .type linkonce_odr_global_program, at object
-; ASM: .section .bss,#alloc,#write
+; ASM: .section .bss,"aw"
; ASM: .weak linkonce_odr_global_program
; ASM: linkonce_odr_global_program:
; ASM: .long 0
diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
index 41551d5fb90606..bb7c43f76c8a13 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
@@ -305,7 +305,7 @@ attributes #4 = { nocallback nofree nosync nounwind speculatable willreturn memo
; Table size length number-kernels * number-variables * sizeof(uint16_t)
; GCN: .type llvm.amdgcn.lds.offset.table, at object
-; GCN-NEXT: .section .data.rel.ro,#alloc,#write
+; GCN-NEXT: .section .data.rel.ro,"aw"
; GCN-NEXT: .p2align 2, 0x0
; GCN-NEXT: llvm.amdgcn.lds.offset.table:
; GCN-NEXT: .long 8
diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
index 38d6039670ab4c..4d73436c519bd2 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
@@ -355,7 +355,7 @@ define amdgpu_kernel void @k123() {
; Table size length number-kernels * number-variables * sizeof(uint16_t)
; GCN: .type llvm.amdgcn.lds.offset.table, at object
-; GCN-NEXT: .section .data.rel.ro,#alloc,#write
+; GCN-NEXT: .section .data.rel.ro,"aw"
; GCN-NEXT: .p2align 4, 0x0
; GCN-NEXT: llvm.amdgcn.lds.offset.table:
; GCN-NEXT: .long 0+4
diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll b/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
index 9ed896c148e648..37209335fc74cf 100644
--- a/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
+++ b/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
@@ -12,7 +12,7 @@ define amdgpu_kernel void @max_alignment_128() #0 {
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
-; VI-NEXT: .section .rodata,#alloc
+; VI-NEXT: .section .rodata,"a"
; VI-NEXT: .p2align 6
; VI-NEXT: .amdhsa_kernel max_alignment_128
; VI-NEXT: .amdhsa_group_segment_fixed_size 0
@@ -60,7 +60,7 @@ define amdgpu_kernel void @max_alignment_128() #0 {
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
-; GFX9-NEXT: .section .rodata,#alloc
+; GFX9-NEXT: .section .rodata,"a"
; GFX9-NEXT: .p2align 6
; GFX9-NEXT: .amdhsa_kernel max_alignment_128
; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
@@ -115,7 +115,7 @@ define amdgpu_kernel void @stackrealign_attr() #1 {
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
-; VI-NEXT: .section .rodata,#alloc
+; VI-NEXT: .section .rodata,"a"
; VI-NEXT: .p2align 6
; VI-NEXT: .amdhsa_kernel stackrealign_attr
; VI-NEXT: .amdhsa_group_segment_fixed_size 0
@@ -163,7 +163,7 @@ define amdgpu_kernel void @stackrealign_attr() #1 {
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
-; GFX9-NEXT: .section .rodata,#alloc
+; GFX9-NEXT: .section .rodata,"a"
; GFX9-NEXT: .p2align 6
; GFX9-NEXT: .amdhsa_kernel stackrealign_attr
; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
@@ -218,7 +218,7 @@ define amdgpu_kernel void @alignstack_attr() #2 {
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
-; VI-NEXT: .section .rodata,#alloc
+; VI-NEXT: .section .rodata,"a"
; VI-NEXT: .p2align 6
; VI-NEXT: .amdhsa_kernel alignstack_attr
; VI-NEXT: .amdhsa_group_segment_fixed_size 0
@@ -266,7 +266,7 @@ define amdgpu_kernel void @alignstack_attr() #2 {
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
-; GFX9-NEXT: .section .rodata,#alloc
+; GFX9-NEXT: .section .rodata,"a"
; GFX9-NEXT: .p2align 6
; GFX9-NEXT: .amdhsa_kernel alignstack_attr
; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
diff --git a/llvm/test/MC/AsmParser/pr64862.s b/llvm/test/MC/AsmParser/pr64862.s
new file mode 100644
index 00000000000000..1e0458129d9963
--- /dev/null
+++ b/llvm/test/MC/AsmParser/pr64862.s
@@ -0,0 +1,4 @@
+; RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu gfx1030 %s | FileCheck %s
+
+; CHECK: .section ".linker-options",#exclude
+ .section ".linker-options",#exclude
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