[llvm] [X86] Support promoted ENQCMD and USER-MSR instructions (PR #77293)

[via llvm-commits]

================
@@ -1523,31 +1523,51 @@ def MOVDIR64B64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$
 // ENQCMD/S - Enqueue 64-byte command as user with 64-byte write atomicity
 //
 let SchedRW = [WriteStore], Defs = [EFLAGS] in {
-  def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src),
+  def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
----------------
XinWang10 wrote:

I think this instruction is similar to movdir64b, as the sde said
> The ENQCMD instruction uses an enqueue store (defined below) to write this command data to the destination
operand. The address of the destination operand is specified in a general-purpose register as an offset into the ES
segment (the segment cannot be overridden).
> In 64-bit mode, the width of the register operand is 64 bits (32 bits with a 67H prefix). Outside 64-bit mode when CS.D = 1, the width is 32 bits (16 bits with a 67H prefix). Outside 64-bit mode when CS.D=0, the width is 16 bits (32 bits with a
67H prefix).
So we use Adsize32 to specify ENQCMD32, and also request the reg size in sib is 32.
And we could validate in xed, the difference of 32/64 is just the prefix 67, we don't have more bits to control 2 reg size.

https://github.com/llvm/llvm-project/pull/77293