[llvm] 478ec63 - [RISCV] Mark VFIRST and VCPOP as SignExtendingOpW (#77022)

[via llvm-commits]

Author: Min-Yih Hsu
Date: 2024-01-08T10:59:06-08:00
New Revision: 478ec63312582c24c8d6ecab280da2380137c0b7

URL: https://github.com/llvm/llvm-project/commit/478ec63312582c24c8d6ecab280da2380137c0b7
DIFF: https://github.com/llvm/llvm-project/commit/478ec63312582c24c8d6ecab280da2380137c0b7.diff

LOG: [RISCV] Mark VFIRST and VCPOP as SignExtendingOpW (#77022)

Since their values are small enough ([-1, 65535] & [0, 65535],
respectively) to fit into signed 32 bits, any sext (or downcasting +
sext) will be redundnat. Hence marking them as SignExtendingOpW.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    llvm/test/CodeGen/RISCV/opt-w-instrs.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 30deeaa064486f..fcb18b67623e7c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -6719,12 +6719,14 @@ defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">;
 // 15.2. Vector mask population count vcpop
 //===----------------------------------------------------------------------===//
 
+let IsSignExtendingOpW = 1 in
 defm PseudoVCPOP: VPseudoVPOP_M;
 
 //===----------------------------------------------------------------------===//
 // 15.3. vfirst find-first-set mask bit
 //===----------------------------------------------------------------------===//
 
+let IsSignExtendingOpW = 1 in
 defm PseudoVFIRST: VPseudoV1ST_M;
 
 //===----------------------------------------------------------------------===//

diff  --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
index 3d25a17a9f7ec7..8c22eaf917e873 100644
--- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
+++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s --check-prefix=CHECK-ZFA
+# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa,+v' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s
 
 ---
 name:            fcvtmod_w_d
@@ -8,13 +8,13 @@ body:             |
   bb.0.entry:
     liveins: $x10
 
-    ; CHECK-ZFA-LABEL: name: fcvtmod_w_d
-    ; CHECK-ZFA: liveins: $x10
-    ; CHECK-ZFA-NEXT: {{  $}}
-    ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10
-    ; CHECK-ZFA-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1
-    ; CHECK-ZFA-NEXT: $x10 = COPY [[FCVTMOD_W_D]]
-    ; CHECK-ZFA-NEXT: PseudoRET
+    ; CHECK-LABEL: name: fcvtmod_w_d
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10
+    ; CHECK-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1
+    ; CHECK-NEXT: $x10 = COPY [[FCVTMOD_W_D]]
+    ; CHECK-NEXT: PseudoRET
     %0:fpr64 = COPY $x10
 
     %1:gpr = nofpexcept FCVTMOD_W_D %0, 1
@@ -30,15 +30,61 @@ body:             |
   bb.0.entry:
     liveins: $x10, $x11
 
-    ; CHECK-ZFA-LABEL: name: physreg
-    ; CHECK-ZFA: liveins: $x10, $x11
-    ; CHECK-ZFA-NEXT: {{  $}}
-    ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
-    ; CHECK-ZFA-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
-    ; CHECK-ZFA-NEXT: $x10 = COPY [[ADDIW]]
-    ; CHECK-ZFA-NEXT: PseudoRET
+    ; CHECK-LABEL: name: physreg
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
+    ; CHECK-NEXT: $x10 = COPY [[ADDIW]]
+    ; CHECK-NEXT: PseudoRET
     %0:gpr = COPY $x10
     %1:gpr = ADDIW %0, 0
     $x10 = COPY %1
     PseudoRET
 ...
+---
+ name:            vfirst
+ tracksRegLiveness: true
+ body:             |
+   bb.0.entry:
+     liveins: $x10, $v8
+
+    ; CHECK-LABEL: name: vfirst
+    ; CHECK: liveins: $x10, $v8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
+    ; CHECK-NEXT: [[PseudoVFIRST_M_B1_:%[0-9]+]]:gpr = PseudoVFIRST_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
+    ; CHECK-NEXT: $x11 = COPY [[PseudoVFIRST_M_B1_]]
+    ; CHECK-NEXT: PseudoRET
+     %0:vr = COPY $v8
+     %1:gprnox0 = COPY $x10
+
+     %2:gpr = PseudoVFIRST_M_B1 %0:vr, %1:gprnox0, 0
+     %3:gpr = ADDIW %2, 0
+     $x11 = COPY %3
+     PseudoRET
+...
+---
+ name:            vcpop
+ tracksRegLiveness: true
+ body:             |
+   bb.0.entry:
+     liveins: $x10, $v8
+
+    ; CHECK-LABEL: name: vcpop
+    ; CHECK: liveins: $x10, $v8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
+    ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
+    ; CHECK-NEXT: $x11 = COPY [[PseudoVCPOP_M_B1_]]
+    ; CHECK-NEXT: PseudoRET
+     %0:vr = COPY $v8
+     %1:gprnox0 = COPY $x10
+
+     %2:gpr = PseudoVCPOP_M_B1 %0:vr, %1:gprnox0, 0
+     %3:gpr = ADDIW %2, 0
+     $x11 = COPY %3
+     PseudoRET
+...