[llvm] [RISCV] Mark VFIRST and VCPOP as SignExtendingOpW (PR #77022)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 8 10:13:08 PST 2024
https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/77022
>From 17d78cfb051924a29e6f10648363205fd73b250e Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Mon, 8 Jan 2024 09:35:37 -0800
Subject: [PATCH 1/3] [RISCV] Mark VFIRST and VCPOP as SignExtendingOpW
Since their values are small enough ([-1, 65535] & [0, 65535],
respectively) to fit into signed 32 bits, any sext (or downcasting +
sext) will be redundnat. Hence marking it as SignExtendingOpW.
---
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 2 +
llvm/test/CodeGen/RISCV/opt-w-instrs.mir | 82 +++++++++++++++----
2 files changed, 69 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 30deeaa064486f..fcb18b67623e7c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -6719,12 +6719,14 @@ defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">;
// 15.2. Vector mask population count vcpop
//===----------------------------------------------------------------------===//
+let IsSignExtendingOpW = 1 in
defm PseudoVCPOP: VPseudoVPOP_M;
//===----------------------------------------------------------------------===//
// 15.3. vfirst find-first-set mask bit
//===----------------------------------------------------------------------===//
+let IsSignExtendingOpW = 1 in
defm PseudoVFIRST: VPseudoV1ST_M;
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
index 3d25a17a9f7ec7..8cf614b3bf6630 100644
--- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
+++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s --check-prefix=CHECK-ZFA
+# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa,+v' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s
---
name: fcvtmod_w_d
@@ -8,13 +8,13 @@ body: |
bb.0.entry:
liveins: $x10
- ; CHECK-ZFA-LABEL: name: fcvtmod_w_d
- ; CHECK-ZFA: liveins: $x10
- ; CHECK-ZFA-NEXT: {{ $}}
- ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10
- ; CHECK-ZFA-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1
- ; CHECK-ZFA-NEXT: $x10 = COPY [[FCVTMOD_W_D]]
- ; CHECK-ZFA-NEXT: PseudoRET
+ ; CHECK-LABEL: name: fcvtmod_w_d
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10
+ ; CHECK-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVTMOD_W_D]]
+ ; CHECK-NEXT: PseudoRET
%0:fpr64 = COPY $x10
%1:gpr = nofpexcept FCVTMOD_W_D %0, 1
@@ -30,15 +30,67 @@ body: |
bb.0.entry:
liveins: $x10, $x11
- ; CHECK-ZFA-LABEL: name: physreg
- ; CHECK-ZFA: liveins: $x10, $x11
- ; CHECK-ZFA-NEXT: {{ $}}
- ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-ZFA-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
- ; CHECK-ZFA-NEXT: $x10 = COPY [[ADDIW]]
- ; CHECK-ZFA-NEXT: PseudoRET
+ ; CHECK-LABEL: name: physreg
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
+ ; CHECK-NEXT: $x10 = COPY [[ADDIW]]
+ ; CHECK-NEXT: PseudoRET
%0:gpr = COPY $x10
%1:gpr = ADDIW %0, 0
$x10 = COPY %1
PseudoRET
...
+---
+ name: vfirst
+ tracksRegLiveness: true
+ body: |
+ bb.0.entry:
+ liveins: $x10, $v8
+
+ ; CHECK-LABEL: name: vfirst
+ ; CHECK: liveins: $x10, $v8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
+ ; CHECK-NEXT: [[PseudoVFIRST_M_B1_:%[0-9]+]]:gpr = PseudoVFIRST_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], [[PseudoVFIRST_M_B1_]]
+ ; CHECK-NEXT: $x10 = COPY [[ADD]]
+ ; CHECK-NEXT: $x11 = COPY [[PseudoVFIRST_M_B1_]]
+ ; CHECK-NEXT: PseudoRET
+ %0:vr = COPY $v8
+ %1:gprnox0 = COPY $x10
+ %2:gpr = PseudoVFIRST_M_B1 %0:vr, %1:gprnox0, 0
+ %3:gpr = ADD %1, %2
+ %4:gpr = ADDIW %2, 0
+ $x10 = COPY %3
+ $x11 = COPY %4
+ PseudoRET
+...
+---
+ name: vcpop
+ tracksRegLiveness: true
+ body: |
+ bb.0.entry:
+ liveins: $x10, $v8
+
+ ; CHECK-LABEL: name: vcpop
+ ; CHECK: liveins: $x10, $v8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
+ ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], [[PseudoVCPOP_M_B1_]]
+ ; CHECK-NEXT: $x10 = COPY [[ADD]]
+ ; CHECK-NEXT: $x11 = COPY [[PseudoVCPOP_M_B1_]]
+ ; CHECK-NEXT: PseudoRET
+ %0:vr = COPY $v8
+ %1:gprnox0 = COPY $x10
+ %2:gpr = PseudoVCPOP_M_B1 %0:vr, %1:gprnox0, 0
+ %3:gpr = ADD %1, %2
+ %4:gpr = ADDIW %2, 0
+ $x10 = COPY %3
+ $x11 = COPY %4
+ PseudoRET
+...
>From 369200a99a15e0b95365b394b52c49d4db21dc78 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Thu, 4 Jan 2024 16:31:38 -0800
Subject: [PATCH 2/3] Use SRLI to create additional use of sext values
---
llvm/test/CodeGen/RISCV/opt-w-instrs.mir | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
index 8cf614b3bf6630..27aad46ab56b95 100644
--- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
+++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
@@ -55,16 +55,15 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[PseudoVFIRST_M_B1_:%[0-9]+]]:gpr = PseudoVFIRST_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], [[PseudoVFIRST_M_B1_]]
- ; CHECK-NEXT: $x10 = COPY [[ADD]]
- ; CHECK-NEXT: $x11 = COPY [[PseudoVFIRST_M_B1_]]
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoVFIRST_M_B1_]], 33
+ ; CHECK-NEXT: $x11 = COPY [[SRLI]]
; CHECK-NEXT: PseudoRET
%0:vr = COPY $v8
%1:gprnox0 = COPY $x10
+
%2:gpr = PseudoVFIRST_M_B1 %0:vr, %1:gprnox0, 0
- %3:gpr = ADD %1, %2
- %4:gpr = ADDIW %2, 0
- $x10 = COPY %3
+ %3:gpr = ADDIW %2, 0
+ %4:gpr = SRLI %3, 33
$x11 = COPY %4
PseudoRET
...
@@ -81,16 +80,15 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], [[PseudoVCPOP_M_B1_]]
- ; CHECK-NEXT: $x10 = COPY [[ADD]]
- ; CHECK-NEXT: $x11 = COPY [[PseudoVCPOP_M_B1_]]
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoVCPOP_M_B1_]], 33
+ ; CHECK-NEXT: $x11 = COPY [[SRLI]]
; CHECK-NEXT: PseudoRET
%0:vr = COPY $v8
%1:gprnox0 = COPY $x10
+
%2:gpr = PseudoVCPOP_M_B1 %0:vr, %1:gprnox0, 0
- %3:gpr = ADD %1, %2
- %4:gpr = ADDIW %2, 0
- $x10 = COPY %3
+ %3:gpr = ADDIW %2, 0
+ %4:gpr = SRLI %3, 33
$x11 = COPY %4
PseudoRET
...
>From b21c7a9e8086b2a0b6bdf947b88e4350359e6638 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Mon, 8 Jan 2024 10:11:15 -0800
Subject: [PATCH 3/3] Use COPY to create artificial uses
---
llvm/test/CodeGen/RISCV/opt-w-instrs.mir | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
index 27aad46ab56b95..8c22eaf917e873 100644
--- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
+++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
@@ -55,16 +55,14 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[PseudoVFIRST_M_B1_:%[0-9]+]]:gpr = PseudoVFIRST_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoVFIRST_M_B1_]], 33
- ; CHECK-NEXT: $x11 = COPY [[SRLI]]
+ ; CHECK-NEXT: $x11 = COPY [[PseudoVFIRST_M_B1_]]
; CHECK-NEXT: PseudoRET
%0:vr = COPY $v8
%1:gprnox0 = COPY $x10
%2:gpr = PseudoVFIRST_M_B1 %0:vr, %1:gprnox0, 0
%3:gpr = ADDIW %2, 0
- %4:gpr = SRLI %3, 33
- $x11 = COPY %4
+ $x11 = COPY %3
PseudoRET
...
---
@@ -80,15 +78,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoVCPOP_M_B1_]], 33
- ; CHECK-NEXT: $x11 = COPY [[SRLI]]
+ ; CHECK-NEXT: $x11 = COPY [[PseudoVCPOP_M_B1_]]
; CHECK-NEXT: PseudoRET
%0:vr = COPY $v8
%1:gprnox0 = COPY $x10
%2:gpr = PseudoVCPOP_M_B1 %0:vr, %1:gprnox0, 0
%3:gpr = ADDIW %2, 0
- %4:gpr = SRLI %3, 33
- $x11 = COPY %4
+ $x11 = COPY %3
PseudoRET
...
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