[llvm] 97e3220 - [InstSimplify] Consider bitcast as potential cross-lane operation

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2024-01-08T15:52:58+01:00
New Revision: 97e3220d6312ae00bcbe08673f218bd0f705776b

URL: https://github.com/llvm/llvm-project/commit/97e3220d6312ae00bcbe08673f218bd0f705776b
DIFF: https://github.com/llvm/llvm-project/commit/97e3220d6312ae00bcbe08673f218bd0f705776b.diff

LOG: [InstSimplify] Consider bitcast as potential cross-lane operation

The bitcast might change the number of vector lanes, in which case
it will be a cross-lane operation.

Fixes https://github.com/llvm/llvm-project/issues/77320.

Added: 
    

Modified: 
    llvm/lib/Analysis/InstructionSimplify.cpp
    llvm/test/Transforms/InstSimplify/select.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp
index 241bdd81b75a97..d0c27cae0dff99 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -4313,7 +4313,7 @@ static Value *simplifyWithOpReplaced(Value *V, Value *Op, Value *RepOp,
     // For vector types, the simplification must hold per-lane, so forbid
     // potentially cross-lane operations like shufflevector.
     if (!I->getType()->isVectorTy() || isa<ShuffleVectorInst>(I) ||
-        isa<CallBase>(I))
+        isa<CallBase>(I) || isa<BitCastInst>(I))
       return nullptr;
   }
 

diff  --git a/llvm/test/Transforms/InstSimplify/select.ll b/llvm/test/Transforms/InstSimplify/select.ll
index 899179e1ccbc22..fe93a0c3f2125e 100644
--- a/llvm/test/Transforms/InstSimplify/select.ll
+++ b/llvm/test/Transforms/InstSimplify/select.ll
@@ -1734,10 +1734,15 @@ define i8 @select_or_disjoint_eq(i8 %x, i8 %y) {
   ret i8 %sel
 }
 
-; FIXME: This is a miscompile.
 define <4 x i32> @select_vector_cmp_with_bitcasts(<2 x i64> %x, <4 x i32> %y) {
 ; CHECK-LABEL: @select_vector_cmp_with_bitcasts(
-; CHECK-NEXT:    ret <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[X_BC:%.*]] = bitcast <2 x i64> [[X:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[Y_BC:%.*]] = bitcast <4 x i32> [[Y:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[SUB:%.*]] = sub <2 x i64> [[X]], [[Y_BC]]
+; CHECK-NEXT:    [[SUB_BC:%.*]] = bitcast <2 x i64> [[SUB]] to <4 x i32>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq <4 x i32> [[Y]], [[X_BC]]
+; CHECK-NEXT:    [[SEL:%.*]] = select <4 x i1> [[CMP]], <4 x i32> [[SUB_BC]], <4 x i32> zeroinitializer
+; CHECK-NEXT:    ret <4 x i32> [[SEL]]
 ;
   %x.bc = bitcast <2 x i64> %x to <4 x i32>
   %y.bc = bitcast <4 x i32> %y to <2 x i64>