[llvm] [AArch64][SVE] Add optimisation for SVE intrinsics with no active lanes (PR #73964)

[Mark Harley via llvm-commits]

MarkAHarley wrote:

> A couple of minor things but otherwise looks good. Do you plan to implement a similar optimisation for the unary instructions?

The optimisation for unary instructions will be in a separate patch.

https://github.com/llvm/llvm-project/pull/73964