[llvm] [RISCV][ISel] Fold trunc (lshr (add (zext X), (zext Y)), 1) -> vaaddu X, Y (PR #76550)

[Luke Lau via llvm-commits]

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@@ -115,6 +124,7 @@ def riscv_saddsat_vl   : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL, [S
 def riscv_uaddsat_vl   : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
 def riscv_ssubsat_vl   : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>;
 def riscv_usubsat_vl   : SDNode<"RISCVISD::USUBSAT_VL", SDT_RISCVIntBinOp_VL>;
+def riscv_uavgadd_vl   : SDNode<"RISCVISD::UAVGADD_VL", SDT_RISCVIntBinOp_RM_VL, [SDNPCommutative]>;
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lukel97 wrote:

I think most of the _vl nodes try to correspond to an SDNode in ISDOpcodes.h. Would it make more sense to instead:

- Mark `ISD::AVGFLOORU` as legal for scalable vector types, and custom for fixed length vector types
- Add a `RISCVISD::AVGFLOORU_VL` node with no rounding mode operand, i.e. it uses`SDT_RISCVIntBinOp_VL`
- Map `ISD::AVGFLOORU` to `RISCVISD::AVGFLOORU_VL` in `getRISCVVLOp`
- In `RISCVTargetLowering::LowerOperation`, add a case for `ISD::AVGFLOORU` beside `ISD::SADDSAT` and friends so fixed length vectors gets lowered via `lowerToScalableOp`
- Add a pattern for `avgflooru` in RISCVInstrInfoVSDPatterns.td, and `riscv_avgflooru_vl` in RISCVInstrInfoVVLPatterns.td, where both select `0b10` for the rounding mode in the pattern output

That way we wouldn't need the custom lowering in `RISCVTargetLowering::lowerUnsignedAvgFloor`, and it would follow the same codegen path as the saturating add and subtract instructions.

https://github.com/llvm/llvm-project/pull/76550