[llvm] [CodeGen][MISched] Add misched post-regalloc bottom-up scheduling (PR #76186)

[Craig Topper via llvm-commits]

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@@ -198,6 +198,7 @@ def SiFive7Model : SchedMachineModel {
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = 0;
+  let PostRAScheduler = true;
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topperc wrote:

This is conceptually a separate change

https://github.com/llvm/llvm-project/pull/76186