[llvm] 61bb3d4 - [X86][NFC] Avoid uselss iterations when emitting EVEX compression table

[Shengchen Kan via llvm-commits]

Author: Shengchen Kan
Date: 2024-01-06T23:53:57+08:00
New Revision: 61bb3d499a234f20b74e70a37a68c0c7d47eb5dc

URL: https://github.com/llvm/llvm-project/commit/61bb3d499a234f20b74e70a37a68c0c7d47eb5dc
DIFF: https://github.com/llvm/llvm-project/commit/61bb3d499a234f20b74e70a37a68c0c7d47eb5dc.diff

LOG: [X86][NFC] Avoid uselss iterations when emitting EVEX compression table

BTW, we relax the condition for EVEX compression from
ST.hasAVX512() to ST.hasEGPR() || ST.hasAVX512(). It does not have any
effect now b/c no APX instruction is in the EVEX compression table so
far.

This patch is to extract NFC in #77065 into a separate commit.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86CompressEVEX.cpp
    llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp
index fc980c611dc67b..07b59437fe2f83 100644
--- a/llvm/lib/Target/X86/X86CompressEVEX.cpp
+++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp
@@ -11,7 +11,7 @@
 //
 // Possible compression:
 //   a. AVX512 instruction (EVEX) -> AVX instruction (VEX)
-//   b. Promoted instruction (EVEX) -> pre-promotion instruction (legacy)
+//   b. Promoted instruction (EVEX) -> pre-promotion instruction (legacy/VEX)
 //   c. NDD (EVEX) -> non-NDD (legacy)
 //   d. NF_ND (EVEX) -> NF (EVEX)
 //
@@ -272,7 +272,7 @@ bool CompressEVEXPass::runOnMachineFunction(MachineFunction &MF) {
   }
 #endif
   const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
-  if (!ST.hasAVX512())
+  if (!ST.hasAVX512() && !ST.hasEGPR())
     return false;
 
   bool Changed = false;

diff  --git a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
index 82a9bfee0115b5..b03bcb6bc26b30 100644
--- a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
@@ -136,7 +136,17 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
   for (const CodeGenInstruction *Inst : NumberedInstructions) {
     const Record *Rec = Inst->TheDef;
     // _REV instruction should not appear before encoding optimization
-    if (!Rec->isSubClassOf("X86Inst") || Rec->getName().ends_with("_REV"))
+    if (!Rec->isSubClassOf("X86Inst") ||
+        Rec->getValueAsBit("isAsmParserOnly") ||
+        Rec->getName().ends_with("_REV"))
+      continue;
+
+    // Promoted legacy instruction is in EVEX space, and has REX2-encoding
+    // alternative. It's added due to HW design and never emitted by compiler.
+    if (byteFromBitsInit(Rec->getValueAsBitsInit("OpMapBits")) ==
+            X86Local::T_MAP4 &&
+        byteFromBitsInit(Rec->getValueAsBitsInit("explicitOpPrefixBits")) ==
+            X86Local::ExplicitEVEX)
       continue;
 
     if (NoCompressSet.find(Rec->getName()) != NoCompressSet.end())