[llvm] [CodeGen][MISched] Add misched post-regalloc bidirectional scheduling (PR #77138)

[via llvm-commits]

github-actions[bot] wrote:

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git-clang-format --diff 058e527434aeb61ee6f72d2d460123440726a7df 343fd1d7b5bb4763f81450b3b7e01a6023ba9ed9 -- llvm/include/llvm/CodeGen/MachineScheduler.h llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h llvm/lib/CodeGen/MachineScheduler.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index b9e6f5c042..46758410a6 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -4025,7 +4025,7 @@ SUnit *PostGenericScheduler::pickNodeBidirectional(bool &IsTopNode) {
       TCand.reset(CandPolicy());
       pickNodeFromQueue(Top, TopCand);
       assert(TCand.SU == TopCand.SU &&
-           "Last pick result should correspond to re-picking right now");
+             "Last pick result should correspond to re-picking right now");
     }
 #endif
   }

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https://github.com/llvm/llvm-project/pull/77138