[llvm] 4dd5d96 - [RISCV] Don't call use_nodbg_operands for physical registers in RISCVOptWInstrs hasAllNBitUsers. (#77032)

[via llvm-commits]

Author: Craig Topper
Date: 2024-01-05T09:22:54-08:00
New Revision: 4dd5d967975fa8d52b8c60596d892d9dd5615809

URL: https://github.com/llvm/llvm-project/commit/4dd5d967975fa8d52b8c60596d892d9dd5615809
DIFF: https://github.com/llvm/llvm-project/commit/4dd5d967975fa8d52b8c60596d892d9dd5615809.diff

LOG: [RISCV] Don't call use_nodbg_operands for physical registers in RISCVOptWInstrs hasAllNBitUsers. (#77032)

The ADDIW in the new test case was incorrectly removed due to
incorrectly following the x10 register from the return value back to the
argument. This is due to use_nodbg_operands returning every instruction
that uses a physical register regardless of the data flow.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
    llvm/test/CodeGen/RISCV/opt-w-instrs.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 2c2b34bb5b7797..c16eee67f3c5c5 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -126,7 +126,11 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
     if (MI->getNumExplicitDefs() != 1)
       return false;
 
-    for (auto &UserOp : MRI.use_nodbg_operands(MI->getOperand(0).getReg())) {
+    Register DestReg = MI->getOperand(0).getReg();
+    if (!DestReg.isVirtual())
+      return false;
+
+    for (auto &UserOp : MRI.use_nodbg_operands(DestReg)) {
       const MachineInstr *UserMI = UserOp.getParent();
       unsigned OpIdx = UserOp.getOperandNo();
 

diff  --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
index 0ecf8fd6bef33a..ebac5a42fbcda0 100644
--- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
+++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
@@ -28,3 +28,23 @@ body:             |
     $x11 = COPY %4
     PseudoRET
 ...
+
+---
+name:            physreg
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; CHECK-ZFA-LABEL: name: physreg
+    ; CHECK-ZFA: liveins: $x10, $x11
+    ; CHECK-ZFA-NEXT: {{  $}}
+    ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-ZFA-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
+    ; CHECK-ZFA-NEXT: $x10 = COPY [[ADDIW]]
+    ; CHECK-ZFA-NEXT: PseudoRET
+    %0:gpr = COPY $x10
+    %1:gpr = ADDIW %0, 0
+    $x10 = COPY %1
+    PseudoRET
+...