[llvm] [JITLink][AArch32] Add TableGen Backend for Instr Encodings (PR #76996)

[Stefan Gränitz via llvm-commits]

https://github.com/weliveindetail commented:

Hello everyone, before we start with detailed reviews, it might be worth mentioning that this is more of a design sketch and not ready to land yet. @eymay Can we mark it as `Draft` please?

I really like the idea of pulling all kinds of data from TableGen! And it's good to see that it can work already for opcodes, masks, register- and immediate bits. Thanks for working on this @eymay! As explained inline, I think the generated structures must still be extensible and one question is how much noise a macro-based approach would add.

Another question is how much linker-specific information can be distilled from TableGen. For example, can TableGen tell us the position of the `BLX` or `H` bits in an ARM `BL` instruction? And otherwise, would it be interesting to add this data to the `.td` files? @smithp35 What do you think?

https://github.com/llvm/llvm-project/pull/76996