[llvm] d187dfe - [AArch64] Add some tests for addLikeOr with csinc. NFC

David Green via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 5 04:39:37 PST 2024


Author: David Green
Date: 2024-01-05T12:39:32Z
New Revision: d187dfe51534b8e15834346ea1898977b7bedace

URL: https://github.com/llvm/llvm-project/commit/d187dfe51534b8e15834346ea1898977b7bedace
DIFF: https://github.com/llvm/llvm-project/commit/d187dfe51534b8e15834346ea1898977b7bedace.diff

LOG: [AArch64] Add some tests for addLikeOr with csinc. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/arm64-csel.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/arm64-csel.ll b/llvm/test/CodeGen/AArch64/arm64-csel.ll
index 35051d0c6017e9..bda0c650910147 100644
--- a/llvm/test/CodeGen/AArch64/arm64-csel.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-csel.ll
@@ -420,3 +420,67 @@ entry:
   ret i64 %add
 }
 
+define i32 @or(i32 %num, i32 %x) {
+; CHECK-LABEL: or:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp w1, #0
+; CHECK-NEXT:    and w8, w0, #0xff00
+; CHECK-NEXT:    cset w9, ne
+; CHECK-NEXT:    orr w0, w8, w9
+; CHECK-NEXT:    ret
+entry:
+  %and = and i32 %num, 65280
+  %tobool.not = icmp ne i32 %x, 0
+  %cond = zext i1 %tobool.not to i32
+  %or = or disjoint i32 %and, %cond
+  ret i32 %or
+}
+
+define i64 @or64(i64 %num, i64 %x) {
+; CHECK-LABEL: or64:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp x1, #0
+; CHECK-NEXT:    and x8, x0, #0xff00
+; CHECK-NEXT:    cset w9, ne
+; CHECK-NEXT:    orr x0, x8, x9
+; CHECK-NEXT:    ret
+entry:
+  %and = and i64 %num, 65280
+  %tobool.not = icmp ne i64 %x, 0
+  %conv = zext i1 %tobool.not to i64
+  %or = or disjoint i64 %and, %conv
+  ret i64 %or
+}
+
+define i32 @selor32(i32 %num, i32 %x) {
+; CHECK-LABEL: selor32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    and w8, w0, #0xff00
+; CHECK-NEXT:    cmp w1, #0
+; CHECK-NEXT:    orr w9, w8, #0x1
+; CHECK-NEXT:    csel w0, w9, w8, ne
+; CHECK-NEXT:    ret
+entry:
+  %and = and i32 %num, 65280
+  %tobool.not = icmp ne i32 %x, 0
+  %or = or disjoint i32 %and, 1
+  %sel = select i1 %tobool.not, i32 %or, i32 %and
+  ret i32 %sel
+}
+
+
+define i64 @selor64(i64 %num, i64 %x) {
+; CHECK-LABEL: selor64:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    and x8, x0, #0xff00
+; CHECK-NEXT:    cmp x1, #0
+; CHECK-NEXT:    orr x9, x8, #0x1
+; CHECK-NEXT:    csel x0, x9, x8, ne
+; CHECK-NEXT:    ret
+entry:
+  %and = and i64 %num, 65280
+  %tobool.not = icmp ne i64 %x, 0
+  %or = or disjoint i64 %and, 1
+  %sel = select i1 %tobool.not, i64 %or, i64 %and
+  ret i64 %sel
+}


        


More information about the llvm-commits mailing list