[llvm] [Mips] Fix missing sign extension in expansion of sub-word atomic max (PR #77072)

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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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``````````bash
git-clang-format --diff b662c9aa0e0580e1fc78a8787414c86ad1984742 e50fd227ef38dafe80e739d36ca39b2186d1ff4c -- llvm/lib/Target/Mips/MipsExpandPseudo.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
index c2a6d52d41..510b2f1a18 100644
--- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
+++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
@@ -483,28 +483,31 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
       BuildMI(loopMBB, DL, TII->get(Mips::AND), Incr).addReg(Incr).addReg(Mask);
 
       if (!IsUnsigned) {
-        BuildMI(loopMBB, DL, TII->get(Mips::SRAV), OldVal).addReg(OldVal).addReg(ShiftAmnt);
-        BuildMI(loopMBB, DL, TII->get(Mips::SRAV), Incr).addReg(Incr).addReg(ShiftAmnt);
+        BuildMI(loopMBB, DL, TII->get(Mips::SRAV), OldVal)
+            .addReg(OldVal)
+            .addReg(ShiftAmnt);
+        BuildMI(loopMBB, DL, TII->get(Mips::SRAV), Incr)
+            .addReg(Incr)
+            .addReg(ShiftAmnt);
         if (STI->hasMips32r2()) {
           BuildMI(loopMBB, DL, TII->get(SEOp), OldVal).addReg(OldVal);
           BuildMI(loopMBB, DL, TII->get(SEOp), Incr).addReg(Incr);
         } else {
           const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24;
           BuildMI(loopMBB, DL, TII->get(Mips::SLL), OldVal)
-            .addReg(OldVal, RegState::Kill)
-            .addImm(ShiftImm);
+              .addReg(OldVal, RegState::Kill)
+              .addImm(ShiftImm);
           BuildMI(loopMBB, DL, TII->get(Mips::SRA), OldVal)
-            .addReg(OldVal, RegState::Kill)
-            .addImm(ShiftImm);
+              .addReg(OldVal, RegState::Kill)
+              .addImm(ShiftImm);
           BuildMI(loopMBB, DL, TII->get(Mips::SLL), Incr)
-            .addReg(Incr, RegState::Kill)
-            .addImm(ShiftImm);
+              .addReg(Incr, RegState::Kill)
+              .addImm(ShiftImm);
           BuildMI(loopMBB, DL, TII->get(Mips::SRA), Incr)
-            .addReg(Incr, RegState::Kill)
-            .addImm(ShiftImm);
+              .addReg(Incr, RegState::Kill)
+              .addImm(ShiftImm);
         }
       }
-
     }
     // unsigned: sltu Scratch4, oldVal, Incr
     // signed:   slt Scratch4, oldVal, Incr

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https://github.com/llvm/llvm-project/pull/77072