[llvm] [X86][MC] Compress APX Promoted instrs from evex to legacy encoding to save code size. (PR #77065)

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git-clang-format --diff f5f66e26b5f010218651cab831d5651fe7a71a0a 10e36ec6f9ed61e8f18a9ace43d62b7169cbe5e5 -- llvm/lib/Target/X86/X86.h llvm/lib/Target/X86/X86InstrInfo.h llvm/lib/Target/X86/X86MCInstLower.cpp llvm/lib/Target/X86/X86TargetMachine.cpp llvm/lib/Target/X86/X86EvexToNonEvex.cpp llvm/utils/TableGen/X86EVEX2NonEVEXTablesEmitter.cpp
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diff --git a/llvm/lib/Target/X86/X86EvexToNonEvex.cpp b/llvm/lib/Target/X86/X86EvexToNonEvex.cpp
index 40470c2129..5d34c266c0 100644
--- a/llvm/lib/Target/X86/X86EvexToNonEvex.cpp
+++ b/llvm/lib/Target/X86/X86EvexToNonEvex.cpp
@@ -206,7 +206,7 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NonEvexOpc) {
   case X86::VRNDSCALESDZm_Int:
   case X86::VRNDSCALESSZr_Int:
   case X86::VRNDSCALESSZm_Int:
-    const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
+    const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
     int64_t ImmVal = Imm.getImm();
     // Ensure that only bits 3:0 of the immediate are used.
     if ((ImmVal & 0xf) != ImmVal)
@@ -273,7 +273,8 @@ static bool CompressEvexToVexImpl(MachineInstr &MI, const X86Subtarget &ST) {
 static bool CompressEVEX2LegacyImpl(MachineInstr &MI, const X86Subtarget &ST) {
   if (!ST.hasEGPR())
     return false;
-  ArrayRef<X86EvexToNonEvexCompressTableEntry> Table = X86EvexToLegacyCompressTable;
+  ArrayRef<X86EvexToNonEvexCompressTableEntry> Table =
+      X86EvexToLegacyCompressTable;
   unsigned EvexOpc = MI.getOpcode();
   const auto *I = llvm::lower_bound(Table, EvexOpc);
   if (I == Table.end() || I->EvexOpc != EvexOpc)

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https://github.com/llvm/llvm-project/pull/77065